Patches contributed by Eötvös Lorand University
commit 948a7b2b5e2bf126fb697aeb11ff379b2c85dd2e
Merge: 9466d6036f73 17483a1f34c9
Author: Ingo Molnar <mingo@elte.hu>
Date: Wed Dec 17 13:16:08 2008 +0100
Merge branch 'irq/sparseirq' into cpus4096
Conflicts:
arch/x86/kernel/io_apic.c
Merge irq/sparseirq here, to resolve conflicts.
diff --cc arch/x86/kernel/io_apic.c
index 60bb8b19f4cd,bfe1245b1a3e..6bd51ce3ce32
--- a/arch/x86/kernel/io_apic.c
+++ b/arch/x86/kernel/io_apic.c
@@@ -249,10 -349,11 +367,12 @@@ static struct irq_cfg *irq_cfg(unsigne
#endif
+ #ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC
-static inline void set_extra_move_desc(struct irq_desc *desc, cpumask_t mask)
+static inline void
+set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
{
}
+ #endif
struct io_apic {
unsigned int index;
@@@ -2402,8 -2485,20 +2536,14 @@@ static void irq_complete_move(struct ir
vector = ~get_irq_regs()->orig_ax;
me = smp_processor_id();
- if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
- cpumask_t cleanup_mask;
-
+ #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
+ *descp = desc = move_irq_desc(desc, me);
+ /* get the new one */
+ cfg = desc->chip_data;
+ #endif
+
- cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
- cfg->move_cleanup_count = cpus_weight(cleanup_mask);
- send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
- cfg->move_in_progress = 0;
- }
+ if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
+ send_cleanup_vector(cfg);
}
#else
static inline void irq_complete_move(struct irq_desc **descp) {}
commit 9466d6036f73481104039fbe99338baed11c8fea
Merge: 1f3f424a6bee 83b19597f793
Author: Ingo Molnar <mingo@elte.hu>
Date: Wed Dec 17 13:08:34 2008 +0100
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/travis/linux-2.6-cpus4096-for-ingo into cpus4096
commit 1f3f424a6bee9de4d839be9951f4296333fac014
Merge: c8cae544bba6 1bda71282ded
Author: Ingo Molnar <mingo@elte.hu>
Date: Wed Dec 17 13:07:48 2008 +0100
Merge branch 'linus' into cpus4096
commit a86ed50859d65a08beec9474df97b88438a996df
Author: Ingo Molnar <mingo@elte.hu>
Date: Wed Dec 17 00:43:10 2008 +0100
perfcounters: use hw_event.disable flag
Impact: implement default-off counters
Make sure that counters that are created with counter.hw_event.disabled=1,
get created in disabled state.
They can be enabled via:
prctl(PR_TASK_PERF_COUNTERS_ENABLE);
Signed-off-by: Ingo Molnar <mingo@elte.hu>
diff --git a/kernel/perf_counter.c b/kernel/perf_counter.c
index 16396e9406fa..5431e790b5d6 100644
--- a/kernel/perf_counter.c
+++ b/kernel/perf_counter.c
@@ -1093,6 +1093,9 @@ perf_counter_alloc(struct perf_counter_hw_event *hw_event,
counter->group_leader = group_leader;
counter->hw_ops = NULL;
+ if (hw_event->disabled)
+ counter->state = PERF_COUNTER_STATE_OFF;
+
hw_ops = NULL;
if (!hw_event->raw && hw_event->type < 0)
hw_ops = sw_perf_counter_init(counter);
commit c15cb37cc4e9809624411333b96109ddf770e29c
Merge: 77be80e437fe 8b1fae4e4200
Author: Ingo Molnar <mingo@elte.hu>
Date: Tue Dec 16 22:53:53 2008 +0100
Merge commit 'v2.6.28-rc8' into x86/uv
commit 78f902ccc597d6ce3e8d1477d70f2d79e960ba7a
Merge: 9ee670fd87b7 8b1fae4e4200
Author: Ingo Molnar <mingo@elte.hu>
Date: Tue Dec 16 22:04:48 2008 +0100
Merge commit 'v2.6.28-rc8' into x86/doc
commit 7e91a122b11bb250d08ab125afd2c232c87502e1
Merge: 1bda71282ded d43779740621
Author: Ingo Molnar <mingo@elte.hu>
Date: Tue Dec 16 21:02:10 2008 +0100
Merge branch 'x86/cpufeature' into x86/tsc
Merge itto in x86/tsc because an upcoming patch relies on a new
cpuid bit defined in the x86/cpufeature branch.
commit d4377974062122d6d9be0bbd8a910a0954714194
Author: Ingo Molnar <mingo@elte.hu>
Date: Tue Dec 16 20:59:24 2008 +0100
x86: support always running TSC on Intel CPUs, add cpufeature definition
Impact: add new synthetic-cpuid bit definition
add X86_FEATURE_NONSTOP_TSC to the cpufeature bits - this is in
preparation of Venki's always-running-TSC patch.
Signed-off-by: Ingo Molnar <mingo@elte.hu>
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 5bce8ed02b44..ea408dcba513 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -92,6 +92,7 @@
#define X86_FEATURE_AMDC1E (3*32+21) /* AMD C1E detected */
#define X86_FEATURE_XTOPOLOGY (3*32+22) /* cpu topology enum extensions */
#define X86_FEATURE_TSC_RELIABLE (3*32+23) /* TSC is known to be reliable */
+#define X86_FEATURE_NONSTOP_TSC (3*32+24) /* TSC does not stop in C states */
/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
#define X86_FEATURE_XMM3 (4*32+ 0) /* "pni" SSE-3 */
commit dd7a5230cd651bfb119d222561c4032f30dd5659
Merge: 050dc6944b9c 8b1fae4e4200
Author: Ingo Molnar <mingo@elte.hu>
Date: Tue Dec 16 20:57:41 2008 +0100
Merge commit 'v2.6.28-rc8' into x86/cpufeature
commit b6fd6f26733e864fba2ea3eb1d716e23d2e66f3a
Author: Ingo Molnar <mingo@elte.hu>
Date: Tue Dec 16 19:23:36 2008 +0100
x86, mm: limit MAXMEM on 64-bit
on 64-bit x86 the physical memory limit is controlled by the sparsemem
bits - which are 44 bits right now. But MAXMEM (the max pfn number
e820 parsing will allow to enter our sizing routines) is set to
0x00003fffffffffff, i.e. 46 bits - that's too large because it overlaps
into the vmalloc range.
So couple MAXMEM to MAX_PHYSMEM_BITS, and add a comment that the
maximum of MAX_PHYSMEM_BITS is 45 bits.
Signed-off-by: Ingo Molnar <mingo@elte.hu>
diff --git a/arch/x86/include/asm/pgtable_64.h b/arch/x86/include/asm/pgtable_64.h
index 65b6be6677c7..c54ba69608bd 100644
--- a/arch/x86/include/asm/pgtable_64.h
+++ b/arch/x86/include/asm/pgtable_64.h
@@ -146,7 +146,7 @@ static inline void native_pgd_clear(pgd_t *pgd)
#define PGDIR_MASK (~(PGDIR_SIZE - 1))
-#define MAXMEM _AC(0x00003fffffffffff, UL)
+#define MAXMEM _AC(__AC(1, UL) << MAX_PHYSMEM_BITS, UL)
#define VMALLOC_START _AC(0xffffc20000000000, UL)
#define VMALLOC_END _AC(0xffffe1ffffffffff, UL)
#define VMEMMAP_START _AC(0xffffe20000000000, UL)
diff --git a/arch/x86/include/asm/sparsemem.h b/arch/x86/include/asm/sparsemem.h
index be44f7dab395..e3cc3c063ec5 100644
--- a/arch/x86/include/asm/sparsemem.h
+++ b/arch/x86/include/asm/sparsemem.h
@@ -27,7 +27,7 @@
#else /* CONFIG_X86_32 */
# define SECTION_SIZE_BITS 27 /* matt - 128 is convenient right now */
# define MAX_PHYSADDR_BITS 44
-# define MAX_PHYSMEM_BITS 44
+# define MAX_PHYSMEM_BITS 44 /* Can be max 45 bits */
#endif
#endif /* CONFIG_SPARSEMEM */