Patches contributed by Eötvös Lorand University
commit e1a94a974c2aa3c0a7c1a915c805211fb6773de1
Author: Ingo Molnar <mingo@elte.hu>
Date: Tue Feb 26 08:51:22 2008 +0100
x86: clean up cpu capabilities accesses, centaur.c
Signed-off-by: Ingo Molnar <mingo@elte.hu>
diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index efe8da88da53..e0f45edd6a55 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -282,12 +282,12 @@ static void __cpuinit init_c3(struct cpuinfo_x86 *c)
rdmsr(MSR_VIA_FCR, lo, hi);
lo |= (1<<1 | 1<<7);
wrmsr(MSR_VIA_FCR, lo, hi);
- set_bit(X86_FEATURE_CX8, c->x86_capability);
+ set_cpu_cap(c, X86_FEATURE_CX8);
}
/* Before Nehemiah, the C3's had 3dNOW! */
if (c->x86_model >= 6 && c->x86_model < 9)
- set_bit(X86_FEATURE_3DNOW, c->x86_capability);
+ set_cpu_cap(c, X86_FEATURE_3DNOW);
get_model_name(c);
display_cacheinfo(c);
@@ -327,7 +327,7 @@ static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
* 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
*/
- clear_bit(0*32+31, c->x86_capability);
+ clear_cpu_cap(c, 0*32+31);
switch (c->x86) {
case 5:
@@ -337,7 +337,7 @@ static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
fcr_set = ECX8|DSMC|EDCTLB|EMMX|ERETSTK;
fcr_clr = DPDC;
printk(KERN_NOTICE "Disabling bugged TSC.\n");
- clear_bit(X86_FEATURE_TSC, c->x86_capability);
+ clear_cpu_cap(c, X86_FEATURE_TSC);
#ifdef CONFIG_X86_OOSTORE
centaur_create_optimal_mcr();
/*
@@ -418,12 +418,12 @@ static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
printk(KERN_INFO "Centaur FCR is 0x%X\n", lo);
}
/* Emulate MTRRs using Centaur's MCR. */
- set_bit(X86_FEATURE_CENTAUR_MCR, c->x86_capability);
+ set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
/* Report CX8 */
- set_bit(X86_FEATURE_CX8, c->x86_capability);
+ set_cpu_cap(c, X86_FEATURE_CX8);
/* Set 3DNow! on Winchip 2 and above. */
if (c->x86_model >= 8)
- set_bit(X86_FEATURE_3DNOW, c->x86_capability);
+ set_cpu_cap(c, X86_FEATURE_3DNOW);
/* See if we can find out some more. */
if (cpuid_eax(0x80000000) >= 0x80000005) {
/* Yes, we can. */
commit 16282a8e25f1783f296e5116dcef810a8e68d1a0
Author: Ingo Molnar <mingo@elte.hu>
Date: Tue Feb 26 08:49:57 2008 +0100
x86: clean up cpu capabilities accesses, amd.c
Signed-off-by: Ingo Molnar <mingo@elte.hu>
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 1a3e1bb4d758..33d38f8305ee 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -68,7 +68,7 @@ static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
if (cpuid_eax(0x80000000) >= 0x80000007) {
c->x86_power = cpuid_edx(0x80000007);
if (c->x86_power & (1<<8))
- set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
+ set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
}
}
@@ -105,9 +105,9 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
/*
* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
- * DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
+ * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
*/
- clear_bit(0*32+31, c->x86_capability);
+ clear_cpu_cap(c, 0*32+31);
r = get_model_name(c);
@@ -131,8 +131,8 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
if (c->x86_model < 6) {
/* Based on AMD doc 20734R - June 2000 */
if (c->x86_model == 0) {
- clear_bit(X86_FEATURE_APIC, c->x86_capability);
- set_bit(X86_FEATURE_PGE, c->x86_capability);
+ clear_cpu_cap(c, X86_FEATURE_APIC);
+ set_cpu_cap(c, X86_FEATURE_PGE);
}
break;
}
@@ -208,7 +208,7 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
/* Set MTRR capability flag if appropriate */
if (c->x86_model == 13 || c->x86_model == 9 ||
(c->x86_model == 8 && c->x86_mask >= 8))
- set_bit(X86_FEATURE_K6_MTRR, c->x86_capability);
+ set_cpu_cap(c, X86_FEATURE_K6_MTRR);
break;
}
@@ -231,7 +231,7 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
rdmsr(MSR_K7_HWCR, l, h);
l &= ~0x00008000;
wrmsr(MSR_K7_HWCR, l, h);
- set_bit(X86_FEATURE_XMM, c->x86_capability);
+ set_cpu_cap(c, X86_FEATURE_XMM);
}
}
@@ -256,14 +256,14 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
/* Use K8 tuning for Fam10h and Fam11h */
case 0x10:
case 0x11:
- set_bit(X86_FEATURE_K8, c->x86_capability);
+ set_cpu_cap(c, X86_FEATURE_K8);
break;
case 6:
- set_bit(X86_FEATURE_K7, c->x86_capability);
+ set_cpu_cap(c, X86_FEATURE_K7);
break;
}
if (c->x86 >= 6)
- set_bit(X86_FEATURE_FXSAVE_LEAK, c->x86_capability);
+ set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
display_cacheinfo(c);
@@ -304,10 +304,10 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
/* K6s reports MCEs but don't actually have all the MSRs */
if (c->x86 < 6)
- clear_bit(X86_FEATURE_MCE, c->x86_capability);
+ clear_cpu_cap(c, X86_FEATURE_MCE);
if (cpu_has_xmm2)
- set_bit(X86_FEATURE_MFENCE_RDTSC, c->x86_capability);
+ set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
}
static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
commit 9716951efd98ada69c417adddc85d9bbe1d7835a
Author: Ingo Molnar <mingo@elte.hu>
Date: Tue Feb 26 08:54:01 2008 +0100
x86: clean up cpu capabilities accesses, generic
Signed-off-by: Ingo Molnar <mingo@elte.hu>
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index ef9e31b89b35..bd111ce8f605 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -374,7 +374,7 @@ static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
#else
c->apicid = (ebx >> 24) & 0xFF;
#endif
- if (c->x86_capability[0] & (1<<19))
+ if (test_cpu_cap(c, X86_FEATURE_CLFLSH))
c->x86_clflush_size = ((ebx >> 8) & 0xff) * 8;
} else {
/* Have CPUID level 0 only - unheard of */
diff --git a/arch/x86/kernel/setup_64.c b/arch/x86/kernel/setup_64.c
index 164200257b68..d65b73e63384 100644
--- a/arch/x86/kernel/setup_64.c
+++ b/arch/x86/kernel/setup_64.c
@@ -687,7 +687,7 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
/* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
- clear_bit(0*32+31, (unsigned long *)&c->x86_capability);
+ clear_cpu_cap(c, 0*32+31);
/* On C+ stepping K8 rep microcode works well for copy/memset */
level = cpuid_eax(1);
@@ -823,7 +823,7 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
{
if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
(c->x86 == 0x6 && c->x86_model >= 0x0e))
- set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
+ set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
}
static void __cpuinit init_intel(struct cpuinfo_x86 *c)
@@ -929,7 +929,7 @@ static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
c->x86 += (tfms >> 20) & 0xff;
if (c->x86 >= 0x6)
c->x86_model += ((tfms >> 16) & 0xF) << 4;
- if (c->x86_capability[0] & (1<<19))
+ if (test_cpu_cap(c, X86_FEATURE_CLFLSH))
c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
} else {
/* Have CPUID level 0 only - unheard of */
commit 0f8d2b926d15a68eac9c19edfdcb58a5d80b2960
Author: Ingo Molnar <mingo@elte.hu>
Date: Tue Feb 26 08:34:21 2008 +0100
x86: clean up cpu capabilities accesses
introduce test_cpu_cap() for raw access to the real CPU
capabilities as they are present in x86_capability.
(cpu_has() will shortcut certain tests during build-time)
Signed-off-by: Ingo Molnar <mingo@elte.hu>
diff --git a/include/asm-x86/cpufeature.h b/include/asm-x86/cpufeature.h
index 065e92966c7c..1e3102eeb823 100644
--- a/include/asm-x86/cpufeature.h
+++ b/include/asm-x86/cpufeature.h
@@ -120,6 +120,9 @@
extern const char * const x86_cap_flags[NCAPINTS*32];
extern const char * const x86_power_flags[32];
+#define test_cpu_cap(c, bit) \
+ test_bit(bit, (unsigned long *)((c)->x86_capability))
+
#define cpu_has(c, bit) \
(__builtin_constant_p(bit) && \
( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) || \
@@ -131,7 +134,8 @@ extern const char * const x86_power_flags[32];
(((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) || \
(((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) ) \
? 1 : \
- test_bit(bit, (unsigned long *)((c)->x86_capability)))
+ test_cpu_cap(c, bit))
+
#define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit)
#define set_cpu_cap(c, bit) set_bit(bit, (unsigned long *)((c)->x86_capability))
commit 513ad84bf60d96a6998bca10ed07c3d340449be8
Author: Ingo Molnar <mingo@elte.hu>
Date: Thu Feb 21 05:18:40 2008 +0100
x86: de-macro start_thread()
Signed-off-by: Ingo Molnar <mingo@elte.hu>
diff --git a/arch/x86/kernel/process_32.c b/arch/x86/kernel/process_32.c
index 2cd89b8a7050..9230ce060d09 100644
--- a/arch/x86/kernel/process_32.c
+++ b/arch/x86/kernel/process_32.c
@@ -512,6 +512,21 @@ int copy_thread(int nr, unsigned long clone_flags, unsigned long sp,
return err;
}
+void
+start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
+{
+ __asm__("movl %0, %%gs" :: "r"(0));
+ regs->fs = 0;
+ set_fs(USER_DS);
+ regs->ds = __USER_DS;
+ regs->es = __USER_DS;
+ regs->ss = __USER_DS;
+ regs->cs = __USER_CS;
+ regs->ip = new_ip;
+ regs->sp = new_sp;
+}
+EXPORT_SYMBOL_GPL(start_thread);
+
#ifdef CONFIG_SECCOMP
static void hard_disable_TSC(void)
{
diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c
index 46c4c546b499..1ffce14cff6e 100644
--- a/arch/x86/kernel/process_64.c
+++ b/arch/x86/kernel/process_64.c
@@ -528,6 +528,21 @@ int copy_thread(int nr, unsigned long clone_flags, unsigned long sp,
return err;
}
+void
+start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
+{
+ asm volatile("movl %0, %%fs; movl %0, %%es; movl %0, %%ds" :: "r"(0));
+ load_gs_index(0);
+ regs->ip = new_ip;
+ regs->sp = new_sp;
+ write_pda(oldrsp, new_sp);
+ regs->cs = __USER_CS;
+ regs->ss = __USER_DS;
+ regs->flags = 0x200;
+ set_fs(USER_DS);
+}
+EXPORT_SYMBOL_GPL(start_thread);
+
/*
* This special macro can be used to load a debugging register
*/
diff --git a/include/asm-x86/processor.h b/include/asm-x86/processor.h
index 43d2cc829a94..9054734589fe 100644
--- a/include/asm-x86/processor.h
+++ b/include/asm-x86/processor.h
@@ -817,20 +817,6 @@ static inline void spin_lock_prefetch(const void *x)
.io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
}
-#define start_thread(regs, new_eip, new_esp) \
-do { \
- __asm__("movl %0,%%gs": :"r" (0)); \
- regs->fs = 0; \
- set_fs(USER_DS); \
- regs->ds = __USER_DS; \
- regs->es = __USER_DS; \
- regs->ss = __USER_DS; \
- regs->cs = __USER_CS; \
- regs->ip = new_eip; \
- regs->sp = new_esp; \
-} while (0)
-
-
extern unsigned long thread_saved_pc(struct task_struct *tsk);
#define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
@@ -887,18 +873,6 @@ extern unsigned long thread_saved_pc(struct task_struct *tsk);
.x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
}
-#define start_thread(regs, new_rip, new_rsp) do { \
- asm volatile("movl %0,%%fs; movl %0,%%es; movl %0,%%ds": :"r" (0)); \
- load_gs_index(0); \
- (regs)->ip = (new_rip); \
- (regs)->sp = (new_rsp); \
- write_pda(oldrsp, (new_rsp)); \
- (regs)->cs = __USER_CS; \
- (regs)->ss = __USER_DS; \
- (regs)->flags = 0x200; \
- set_fs(USER_DS); \
-} while (0)
-
/*
* Return saved PC of a blocked thread.
* What is this good for? it will be always the scheduler or ret_from_fork.
@@ -909,6 +883,9 @@ extern unsigned long thread_saved_pc(struct task_struct *tsk);
#define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */
#endif /* CONFIG_X86_64 */
+extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
+ unsigned long new_sp);
+
/*
* This decides where the kernel will search for a free chunk of vm
* space during mmap's.
commit 1180e01de50c0c7683c6648251f32957bc2d7850
Author: Ingo Molnar <mingo@elte.hu>
Date: Thu Feb 21 05:03:48 2008 +0100
x86: more cleanups in arch/x86/boot/compressed/misc.c
Before:
total: 7 errors, 8 warnings, 471 lines checked
After:
total: 5 errors, 5 warnings, 479 lines checked
( the rest cannot be eliminated due to zlib interface cruftiness. )
No code changed:
arch/x86/boot/compressed/misc.o:
text data bss dec hex filename
10716 8 2152 12876 324c misc.o.before
10716 8 2152 12876 324c misc.o.after
md5:
2c20c903986a3c9bca44306c6646067e misc.o.before.asm
2c20c903986a3c9bca44306c6646067e misc.o.after.asm
Signed-off-by: Ingo Molnar <mingo@elte.hu>
diff --git a/arch/x86/boot/compressed/misc.c b/arch/x86/boot/compressed/misc.c
index 50d054c29018..9470a050f8a4 100644
--- a/arch/x86/boot/compressed/misc.c
+++ b/arch/x86/boot/compressed/misc.c
@@ -58,8 +58,8 @@
* 1 bit (last block flag)
* 2 bits (block type)
*
- * 1 block occurs every 32K -1 bytes or when there 50% compression has been achieved.
- * The smallest block type encoding is always used.
+ * 1 block occurs every 32K -1 bytes or when there 50% compression
+ * has been achieved. The smallest block type encoding is always used.
*
* stored:
* 32 bits length in bytes.
@@ -95,9 +95,9 @@
*
* All of which is enough to compute an amount of extra data that is required
* to be safe. To avoid problems at the block level allocating 5 extra bytes
- * per 32767 bytes of data is sufficient. To avoind problems internal to a block
- * adding an extra 32767 bytes (the worst case uncompressed block size) is
- * sufficient, to ensure that in the worst case the decompressed data for
+ * per 32767 bytes of data is sufficient. To avoind problems internal to a
+ * block adding an extra 32767 bytes (the worst case uncompressed block size)
+ * is sufficient, to ensure that in the worst case the decompressed data for
* block will stop the byte before the compressed data for a block begins.
* To avoid problems with the compressed data's meta information an extra 18
* bytes are needed. Leading to the formula:
@@ -116,52 +116,59 @@
* gzip declarations
*/
-#define OF(args) args
-#define STATIC static
+#define OF(args) args
+#define STATIC static
#undef memset
#undef memcpy
-#define memzero(s, n) memset ((s), 0, (n))
+#define memzero(s, n) memset((s), 0, (n))
-typedef unsigned char uch;
-typedef unsigned short ush;
-typedef unsigned long ulg;
+typedef unsigned char uch;
+typedef unsigned short ush;
+typedef unsigned long ulg;
-#define WSIZE 0x80000000 /*
- * Window size must be at least 32k,
- * and a power of two
- * We don't actually have a window just
- * a huge output buffer so I report
- * a 2G windows size, as that should
- * always be larger than our output buffer.
- */
+/*
+ * Window size must be at least 32k, and a power of two.
+ * We don't actually have a window just a huge output buffer,
+ * so we report a 2G window size, as that should always be
+ * larger than our output buffer:
+ */
+#define WSIZE 0x80000000
+
+/* Input buffer: */
+static unsigned char *inbuf;
+
+/* Sliding window buffer (and final output buffer): */
+static unsigned char *window;
+
+/* Valid bytes in inbuf: */
+static unsigned insize;
-static uch *inbuf; /* input buffer */
-static uch *window; /* Sliding window buffer, (and final output buffer) */
+/* Index of next byte to be processed in inbuf: */
+static unsigned inptr;
-static unsigned insize; /* valid bytes in inbuf */
-static unsigned inptr; /* index of next byte to be processed in inbuf */
-static unsigned outcnt; /* bytes in output buffer */
+/* Bytes in output buffer: */
+static unsigned outcnt;
/* gzip flag byte */
-#define ASCII_FLAG 0x01 /* bit 0 set: file probably ASCII text */
-#define CONTINUATION 0x02 /* bit 1 set: continuation of multi-part gzip file */
-#define EXTRA_FIELD 0x04 /* bit 2 set: extra field present */
-#define ORIG_NAME 0x08 /* bit 3 set: original file name present */
-#define COMMENT 0x10 /* bit 4 set: file comment present */
-#define ENCRYPTED 0x20 /* bit 5 set: file is encrypted */
-#define RESERVED 0xC0 /* bit 6,7: reserved */
+#define ASCII_FLAG 0x01 /* bit 0 set: file probably ASCII text */
+#define CONTINUATION 0x02 /* bit 1 set: continuation of multi-part gz file */
+#define EXTRA_FIELD 0x04 /* bit 2 set: extra field present */
+#define ORIG_NAM 0x08 /* bit 3 set: original file name present */
+#define COMMENT 0x10 /* bit 4 set: file comment present */
+#define ENCRYPTED 0x20 /* bit 5 set: file is encrypted */
+#define RESERVED 0xC0 /* bit 6, 7: reserved */
-#define get_byte() (inptr < insize ? inbuf[inptr++] : fill_inbuf())
+#define get_byte() (inptr < insize ? inbuf[inptr++] : fill_inbuf())
/* Diagnostic functions */
#ifdef DEBUG
-# define Assert(cond, msg) {if(!(cond)) error(msg); }
-# define Trace(x) fprintf x
-# define Tracev(x) {if (verbose) fprintf x ; }
-# define Tracevv(x) {if (verbose > 1) fprintf x ; }
-# define Tracec(c, x) {if (verbose && (c)) fprintf x ; }
-# define Tracecv(c, x) {if (verbose > 1 && (c)) fprintf x ; }
+# define Assert(cond, msg) do { if (!(cond)) error(msg); } while (0)
+# define Trace(x) do { fprintf x; } while (0)
+# define Tracev(x) do { if (verbose) fprintf x ; } while (0)
+# define Tracevv(x) do { if (verbose > 1) fprintf x ; } while (0)
+# define Tracec(c, x) do { if (verbose && (c)) fprintf x ; } while (0)
+# define Tracecv(c, x) do { if (verbose > 1 && (c)) fprintf x ; } while (0)
#else
# define Assert(cond, msg)
# define Trace(x)
@@ -349,9 +356,9 @@ static void flush_window(void)
/* With my window equal to my output buffer
* I only need to compute the crc here.
*/
- ulg c = crc; /* temporary variable */
+ unsigned long c = crc; /* temporary variable */
unsigned n;
- uch *in, ch;
+ unsigned char *in, ch;
in = window;
for (n = 0; n < outcnt; n++) {
@@ -359,7 +366,7 @@ static void flush_window(void)
c = crc_32_tab[((int)c ^ ch) & 0xff] ^ (c >> 8);
}
crc = c;
- bytes_out += (ulg)outcnt;
+ bytes_out += (unsigned long)outcnt;
outcnt = 0;
}
@@ -423,8 +430,9 @@ static void parse_elf(void *output)
}
asmlinkage void decompress_kernel(void *rmode, memptr heap,
- uch *input_data, unsigned long input_len,
- uch *output)
+ unsigned char *input_data,
+ unsigned long input_len,
+ unsigned char *output)
{
real_mode = rmode;
@@ -447,12 +455,12 @@ asmlinkage void decompress_kernel(void *rmode, memptr heap,
inptr = 0;
#ifdef CONFIG_X86_64
- if ((ulg)output & (__KERNEL_ALIGN - 1))
+ if ((unsigned long)output & (__KERNEL_ALIGN - 1))
error("Destination address not 2M aligned");
- if ((ulg)output >= 0xffffffffffUL)
+ if ((unsigned long)output >= 0xffffffffffUL)
error("Destination address too large");
#else
- if ((u32)output & (CONFIG_PHYSICAL_ALIGN -1))
+ if ((u32)output & (CONFIG_PHYSICAL_ALIGN - 1))
error("Destination address not CONFIG_PHYSICAL_ALIGN aligned");
if (heap > ((-__PAGE_OFFSET-(512<<20)-1) & 0x7fffffff))
error("Destination address too large");
commit 4d46a89e7c867718020b2d5fd8f9e775293304be
Author: Ingo Molnar <mingo@elte.hu>
Date: Thu Feb 21 04:24:40 2008 +0100
x86: clean up include/asm-x86/processor.h
basic style cleanup to flush out years of neglect:
- consistent indentation
- whitespace fixes
- consistent comments
Signed-off-by: Ingo Molnar <mingo@elte.hu>
diff --git a/include/asm-x86/processor.h b/include/asm-x86/processor.h
index 45a2f0ab33d0..43d2cc829a94 100644
--- a/include/asm-x86/processor.h
+++ b/include/asm-x86/processor.h
@@ -24,6 +24,7 @@ struct mm_struct;
#include <asm/msr.h>
#include <asm/desc_defs.h>
#include <asm/nops.h>
+
#include <linux/personality.h>
#include <linux/cpumask.h>
#include <linux/cache.h>
@@ -37,16 +38,18 @@ struct mm_struct;
static inline void *current_text_addr(void)
{
void *pc;
- asm volatile("mov $1f,%0\n1:":"=r" (pc));
+
+ asm volatile("mov $1f, %0; 1:":"=r" (pc));
+
return pc;
}
#ifdef CONFIG_X86_VSMP
-#define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
-#define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
+# define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
+# define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
#else
-#define ARCH_MIN_TASKALIGN 16
-#define ARCH_MIN_MMSTRUCT_ALIGN 0
+# define ARCH_MIN_TASKALIGN 16
+# define ARCH_MIN_MMSTRUCT_ALIGN 0
#endif
/*
@@ -56,69 +59,81 @@ static inline void *current_text_addr(void)
*/
struct cpuinfo_x86 {
- __u8 x86; /* CPU family */
- __u8 x86_vendor; /* CPU vendor */
- __u8 x86_model;
- __u8 x86_mask;
+ __u8 x86; /* CPU family */
+ __u8 x86_vendor; /* CPU vendor */
+ __u8 x86_model;
+ __u8 x86_mask;
#ifdef CONFIG_X86_32
- char wp_works_ok; /* It doesn't on 386's */
- char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
- char hard_math;
- char rfu;
- char fdiv_bug;
- char f00f_bug;
- char coma_bug;
- char pad0;
+ char wp_works_ok; /* It doesn't on 386's */
+
+ /* Problems on some 486Dx4's and old 386's: */
+ char hlt_works_ok;
+ char hard_math;
+ char rfu;
+ char fdiv_bug;
+ char f00f_bug;
+ char coma_bug;
+ char pad0;
#else
- /* number of 4K pages in DTLB/ITLB combined(in pages)*/
- int x86_tlbsize;
- __u8 x86_virt_bits, x86_phys_bits;
- /* cpuid returned core id bits */
- __u8 x86_coreid_bits;
- /* Max extended CPUID function supported */
- __u32 extended_cpuid_level;
+ /* Number of 4K pages in DTLB/ITLB combined(in pages): */
+ int x86_tlbsize;
+ __u8 x86_virt_bits;
+ __u8 x86_phys_bits;
+ /* CPUID returned core id bits: */
+ __u8 x86_coreid_bits;
+ /* Max extended CPUID function supported: */
+ __u32 extended_cpuid_level;
#endif
- int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
- __u32 x86_capability[NCAPINTS];
- char x86_vendor_id[16];
- char x86_model_id[64];
- int x86_cache_size; /* in KB - valid for CPUS which support this
- call */
- int x86_cache_alignment; /* In bytes */
- int x86_power;
- unsigned long loops_per_jiffy;
+ /* Maximum supported CPUID level, -1=no CPUID: */
+ int cpuid_level;
+ __u32 x86_capability[NCAPINTS];
+ char x86_vendor_id[16];
+ char x86_model_id[64];
+ /* in KB - valid for CPUS which support this call: */
+ int x86_cache_size;
+ int x86_cache_alignment; /* In bytes */
+ int x86_power;
+ unsigned long loops_per_jiffy;
#ifdef CONFIG_SMP
- cpumask_t llc_shared_map; /* cpus sharing the last level cache */
+ /* cpus sharing the last level cache: */
+ cpumask_t llc_shared_map;
#endif
- u16 x86_max_cores; /* cpuid returned max cores value */
- u16 apicid;
- u16 x86_clflush_size;
+ /* cpuid returned max cores value: */
+ u16 x86_max_cores;
+ u16 apicid;
+ u16 x86_clflush_size;
#ifdef CONFIG_SMP
- u16 booted_cores; /* number of cores as seen by OS */
- u16 phys_proc_id; /* Physical processor id. */
- u16 cpu_core_id; /* Core id */
- u16 cpu_index; /* index into per_cpu list */
+ /* number of cores as seen by the OS: */
+ u16 booted_cores;
+ /* Physical processor id: */
+ u16 phys_proc_id;
+ /* Core id: */
+ u16 cpu_core_id;
+ /* Index into per_cpu list: */
+ u16 cpu_index;
#endif
} __attribute__((__aligned__(SMP_CACHE_BYTES)));
-#define X86_VENDOR_INTEL 0
-#define X86_VENDOR_CYRIX 1
-#define X86_VENDOR_AMD 2
-#define X86_VENDOR_UMC 3
-#define X86_VENDOR_NEXGEN 4
-#define X86_VENDOR_CENTAUR 5
-#define X86_VENDOR_TRANSMETA 7
-#define X86_VENDOR_NSC 8
-#define X86_VENDOR_NUM 9
-#define X86_VENDOR_UNKNOWN 0xff
+#define X86_VENDOR_INTEL 0
+#define X86_VENDOR_CYRIX 1
+#define X86_VENDOR_AMD 2
+#define X86_VENDOR_UMC 3
+#define X86_VENDOR_NEXGEN 4
+#define X86_VENDOR_CENTAUR 5
+#define X86_VENDOR_TRANSMETA 7
+#define X86_VENDOR_NSC 8
+#define X86_VENDOR_NUM 9
+
+#define X86_VENDOR_UNKNOWN 0xff
/*
* capabilities of CPUs
*/
-extern struct cpuinfo_x86 boot_cpu_data;
-extern struct cpuinfo_x86 new_cpu_data;
-extern struct tss_struct doublefault_tss;
-extern __u32 cleared_cpu_caps[NCAPINTS];
+extern struct cpuinfo_x86 boot_cpu_data;
+extern struct cpuinfo_x86 new_cpu_data;
+
+extern struct tss_struct doublefault_tss;
+extern __u32 cleared_cpu_caps[NCAPINTS];
#ifdef CONFIG_SMP
DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
@@ -129,7 +144,9 @@ DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
#define current_cpu_data boot_cpu_data
#endif
-void cpu_detect(struct cpuinfo_x86 *c);
+#define cache_line_size() (boot_cpu_data.x86_cache_alignment)
+
+extern void cpu_detect(struct cpuinfo_x86 *c);
extern void identify_cpu(struct cpuinfo_x86 *);
extern void identify_boot_cpu(void);
@@ -146,7 +163,7 @@ static inline void detect_ht(struct cpuinfo_x86 *c) {}
#endif
static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
- unsigned int *ecx, unsigned int *edx)
+ unsigned int *ecx, unsigned int *edx)
{
/* ecx is often an input as well as an output. */
__asm__("cpuid"
@@ -165,54 +182,67 @@ static inline void load_cr3(pgd_t *pgdir)
#ifdef CONFIG_X86_32
/* This is the TSS defined by the hardware. */
struct x86_hw_tss {
- unsigned short back_link, __blh;
- unsigned long sp0;
- unsigned short ss0, __ss0h;
- unsigned long sp1;
- unsigned short ss1, __ss1h; /* ss1 caches MSR_IA32_SYSENTER_CS */
- unsigned long sp2;
- unsigned short ss2, __ss2h;
- unsigned long __cr3;
- unsigned long ip;
- unsigned long flags;
- unsigned long ax, cx, dx, bx;
- unsigned long sp, bp, si, di;
- unsigned short es, __esh;
- unsigned short cs, __csh;
- unsigned short ss, __ssh;
- unsigned short ds, __dsh;
- unsigned short fs, __fsh;
- unsigned short gs, __gsh;
- unsigned short ldt, __ldth;
- unsigned short trace, io_bitmap_base;
+ unsigned short back_link, __blh;
+ unsigned long sp0;
+ unsigned short ss0, __ss0h;
+ unsigned long sp1;
+ /* ss1 caches MSR_IA32_SYSENTER_CS: */
+ unsigned short ss1, __ss1h;
+ unsigned long sp2;
+ unsigned short ss2, __ss2h;
+ unsigned long __cr3;
+ unsigned long ip;
+ unsigned long flags;
+ unsigned long ax;
+ unsigned long cx;
+ unsigned long dx;
+ unsigned long bx;
+ unsigned long sp;
+ unsigned long bp;
+ unsigned long si;
+ unsigned long di;
+ unsigned short es, __esh;
+ unsigned short cs, __csh;
+ unsigned short ss, __ssh;
+ unsigned short ds, __dsh;
+ unsigned short fs, __fsh;
+ unsigned short gs, __gsh;
+ unsigned short ldt, __ldth;
+ unsigned short trace;
+ unsigned short io_bitmap_base;
+
} __attribute__((packed));
#else
struct x86_hw_tss {
- u32 reserved1;
- u64 sp0;
- u64 sp1;
- u64 sp2;
- u64 reserved2;
- u64 ist[7];
- u32 reserved3;
- u32 reserved4;
- u16 reserved5;
- u16 io_bitmap_base;
+ u32 reserved1;
+ u64 sp0;
+ u64 sp1;
+ u64 sp2;
+ u64 reserved2;
+ u64 ist[7];
+ u32 reserved3;
+ u32 reserved4;
+ u16 reserved5;
+ u16 io_bitmap_base;
+
} __attribute__((packed)) ____cacheline_aligned;
#endif
/*
- * Size of io_bitmap.
+ * IO-bitmap sizes:
*/
-#define IO_BITMAP_BITS 65536
-#define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
-#define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
-#define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
-#define INVALID_IO_BITMAP_OFFSET 0x8000
-#define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
+#define IO_BITMAP_BITS 65536
+#define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
+#define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
+#define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
+#define INVALID_IO_BITMAP_OFFSET 0x8000
+#define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
struct tss_struct {
- struct x86_hw_tss x86_tss;
+ /*
+ * The hardware state:
+ */
+ struct x86_hw_tss x86_tss;
/*
* The extra 1 is there because the CPU will access an
@@ -220,48 +250,54 @@ struct tss_struct {
* bitmap. The extra byte must be all 1 bits, and must
* be within the limit.
*/
- unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
+ unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
/*
* Cache the current maximum and the last task that used the bitmap:
*/
- unsigned long io_bitmap_max;
- struct thread_struct *io_bitmap_owner;
+ unsigned long io_bitmap_max;
+ struct thread_struct *io_bitmap_owner;
+
/*
- * pads the TSS to be cacheline-aligned (size is 0x100)
+ * Pad the TSS to be cacheline-aligned (size is 0x100):
*/
- unsigned long __cacheline_filler[35];
+ unsigned long __cacheline_filler[35];
/*
- * .. and then another 0x100 bytes for emergency kernel stack
+ * .. and then another 0x100 bytes for the emergency kernel stack:
*/
- unsigned long stack[64];
+ unsigned long stack[64];
+
} __attribute__((packed));
DECLARE_PER_CPU(struct tss_struct, init_tss);
-/* Save the original ist values for checking stack pointers during debugging */
+/*
+ * Save the original ist values for checking stack pointers during debugging
+ */
struct orig_ist {
- unsigned long ist[7];
+ unsigned long ist[7];
};
#define MXCSR_DEFAULT 0x1f80
struct i387_fsave_struct {
- u32 cwd;
- u32 swd;
- u32 twd;
- u32 fip;
- u32 fcs;
- u32 foo;
- u32 fos;
- u32 st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
- u32 status; /* software status information */
+ u32 cwd;
+ u32 swd;
+ u32 twd;
+ u32 fip;
+ u32 fcs;
+ u32 foo;
+ u32 fos;
+ /* 8*10 bytes for each FP-reg = 80 bytes: */
+ u32 st_space[20];
+ /* Software status information: */
+ u32 status;
};
struct i387_fxsave_struct {
- u16 cwd;
- u16 swd;
- u16 twd;
- u16 fop;
+ u16 cwd;
+ u16 swd;
+ u16 twd;
+ u16 fop;
union {
struct {
u64 rip;
@@ -274,31 +310,40 @@ struct i387_fxsave_struct {
u32 fos;
};
};
- u32 mxcsr;
- u32 mxcsr_mask;
- u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
- u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
- u32 padding[24];
+ u32 mxcsr;
+ u32 mxcsr_mask;
+ /* 8*16 bytes for each FP-reg = 128 bytes: */
+ u32 st_space[32];
+ /* 16*16 bytes for each XMM-reg = 256 bytes: */
+ u32 xmm_space[64];
+ u32 padding[24];
+
} __attribute__((aligned(16)));
struct i387_soft_struct {
- u32 cwd;
- u32 swd;
- u32 twd;
- u32 fip;
- u32 fcs;
- u32 foo;
- u32 fos;
- u32 st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
- u8 ftop, changed, lookahead, no_update, rm, alimit;
- struct info *info;
- u32 entry_eip;
+ u32 cwd;
+ u32 swd;
+ u32 twd;
+ u32 fip;
+ u32 fcs;
+ u32 foo;
+ u32 fos;
+ /* 8*10 bytes for each FP-reg = 80 bytes: */
+ u32 st_space[20];
+ u8 ftop;
+ u8 changed;
+ u8 lookahead;
+ u8 no_update;
+ u8 rm;
+ u8 alimit;
+ struct info *info;
+ u32 entry_eip;
};
union i387_union {
struct i387_fsave_struct fsave;
struct i387_fxsave_struct fxsave;
- struct i387_soft_struct soft;
+ struct i387_soft_struct soft;
};
#ifdef CONFIG_X86_32
@@ -313,42 +358,50 @@ extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
extern unsigned short num_cache_leaves;
struct thread_struct {
-/* cached TLS descriptors. */
- struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
- unsigned long sp0;
- unsigned long sp;
+ /* Cached TLS descriptors: */
+ struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
+ unsigned long sp0;
+ unsigned long sp;
#ifdef CONFIG_X86_32
- unsigned long sysenter_cs;
+ unsigned long sysenter_cs;
#else
- unsigned long usersp; /* Copy from PDA */
- unsigned short es, ds, fsindex, gsindex;
+ unsigned long usersp; /* Copy from PDA */
+ unsigned short es;
+ unsigned short ds;
+ unsigned short fsindex;
+ unsigned short gsindex;
#endif
- unsigned long ip;
- unsigned long fs;
- unsigned long gs;
-/* Hardware debugging registers */
- unsigned long debugreg0;
- unsigned long debugreg1;
- unsigned long debugreg2;
- unsigned long debugreg3;
- unsigned long debugreg6;
- unsigned long debugreg7;
-/* fault info */
- unsigned long cr2, trap_no, error_code;
-/* floating point info */
+ unsigned long ip;
+ unsigned long fs;
+ unsigned long gs;
+ /* Hardware debugging registers: */
+ unsigned long debugreg0;
+ unsigned long debugreg1;
+ unsigned long debugreg2;
+ unsigned long debugreg3;
+ unsigned long debugreg6;
+ unsigned long debugreg7;
+ /* Fault info: */
+ unsigned long cr2;
+ unsigned long trap_no;
+ unsigned long error_code;
+ /* Floating point info: */
union i387_union i387 __attribute__((aligned(16)));;
#ifdef CONFIG_X86_32
-/* virtual 86 mode info */
+ /* Virtual 86 mode info */
struct vm86_struct __user *vm86_info;
unsigned long screen_bitmap;
- unsigned long v86flags, v86mask, saved_sp0;
- unsigned int saved_fs, saved_gs;
+ unsigned long v86flags;
+ unsigned long v86mask;
+ unsigned long saved_sp0;
+ unsigned int saved_fs;
+ unsigned int saved_gs;
#endif
-/* IO permissions */
- unsigned long *io_bitmap_ptr;
- unsigned long iopl;
-/* max allowed port in the bitmap, in bytes: */
- unsigned io_bitmap_max;
+ /* IO permissions: */
+ unsigned long *io_bitmap_ptr;
+ unsigned long iopl;
+ /* Max allowed port in the bitmap, in bytes: */
+ unsigned io_bitmap_max;
/* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */
unsigned long debugctlmsr;
/* Debug Store - if not 0 points to a DS Save Area configuration;
@@ -358,7 +411,7 @@ struct thread_struct {
static inline unsigned long native_get_debugreg(int regno)
{
- unsigned long val = 0; /* Damn you, gcc! */
+ unsigned long val = 0; /* Damn you, gcc! */
switch (regno) {
case 0:
@@ -383,22 +436,22 @@ static inline void native_set_debugreg(int regno, unsigned long value)
{
switch (regno) {
case 0:
- asm("mov %0,%%db0" : /* no output */ :"r" (value));
+ asm("mov %0, %%db0" ::"r" (value));
break;
case 1:
- asm("mov %0,%%db1" : /* no output */ :"r" (value));
+ asm("mov %0, %%db1" ::"r" (value));
break;
case 2:
- asm("mov %0,%%db2" : /* no output */ :"r" (value));
+ asm("mov %0, %%db2" ::"r" (value));
break;
case 3:
- asm("mov %0,%%db3" : /* no output */ :"r" (value));
+ asm("mov %0, %%db3" ::"r" (value));
break;
case 6:
- asm("mov %0,%%db6" : /* no output */ :"r" (value));
+ asm("mov %0, %%db6" ::"r" (value));
break;
case 7:
- asm("mov %0,%%db7" : /* no output */ :"r" (value));
+ asm("mov %0, %%db7" ::"r" (value));
break;
default:
BUG();
@@ -412,6 +465,7 @@ static inline void native_set_iopl_mask(unsigned mask)
{
#ifdef CONFIG_X86_32
unsigned int reg;
+
__asm__ __volatile__ ("pushfl;"
"popl %0;"
"andl %1, %0;"
@@ -423,12 +477,12 @@ static inline void native_set_iopl_mask(unsigned mask)
#endif
}
-static inline void native_load_sp0(struct tss_struct *tss,
- struct thread_struct *thread)
+static inline void
+native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
{
tss->x86_tss.sp0 = thread->sp0;
#ifdef CONFIG_X86_32
- /* Only happens when SEP is enabled, no need to test "SEP"arately */
+ /* Only happens when SEP is enabled, no need to test "SEP"arately: */
if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
tss->x86_tss.ss1 = thread->sysenter_cs;
wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
@@ -446,8 +500,8 @@ static inline void native_swapgs(void)
#ifdef CONFIG_PARAVIRT
#include <asm/paravirt.h>
#else
-#define __cpuid native_cpuid
-#define paravirt_enabled() 0
+#define __cpuid native_cpuid
+#define paravirt_enabled() 0
/*
* These special macros can be used to get or set a debugging register
@@ -457,8 +511,8 @@ static inline void native_swapgs(void)
#define set_debugreg(value, register) \
native_set_debugreg(register, value)
-static inline void load_sp0(struct tss_struct *tss,
- struct thread_struct *thread)
+static inline void
+load_sp0(struct tss_struct *tss, struct thread_struct *thread)
{
native_load_sp0(tss, thread);
}
@@ -473,11 +527,12 @@ static inline void load_sp0(struct tss_struct *tss,
* enable), so that any CPU's that boot up
* after us can get the correct flags.
*/
-extern unsigned long mmu_cr4_features;
+extern unsigned long mmu_cr4_features;
static inline void set_in_cr4(unsigned long mask)
{
unsigned cr4;
+
mmu_cr4_features |= mask;
cr4 = read_cr4();
cr4 |= mask;
@@ -487,6 +542,7 @@ static inline void set_in_cr4(unsigned long mask)
static inline void clear_in_cr4(unsigned long mask)
{
unsigned cr4;
+
mmu_cr4_features &= ~mask;
cr4 = read_cr4();
cr4 &= ~mask;
@@ -494,42 +550,42 @@ static inline void clear_in_cr4(unsigned long mask)
}
struct microcode_header {
- unsigned int hdrver;
- unsigned int rev;
- unsigned int date;
- unsigned int sig;
- unsigned int cksum;
- unsigned int ldrver;
- unsigned int pf;
- unsigned int datasize;
- unsigned int totalsize;
- unsigned int reserved[3];
+ unsigned int hdrver;
+ unsigned int rev;
+ unsigned int date;
+ unsigned int sig;
+ unsigned int cksum;
+ unsigned int ldrver;
+ unsigned int pf;
+ unsigned int datasize;
+ unsigned int totalsize;
+ unsigned int reserved[3];
};
struct microcode {
- struct microcode_header hdr;
- unsigned int bits[0];
+ struct microcode_header hdr;
+ unsigned int bits[0];
};
-typedef struct microcode microcode_t;
-typedef struct microcode_header microcode_header_t;
+typedef struct microcode microcode_t;
+typedef struct microcode_header microcode_header_t;
/* microcode format is extended from prescott processors */
struct extended_signature {
- unsigned int sig;
- unsigned int pf;
- unsigned int cksum;
+ unsigned int sig;
+ unsigned int pf;
+ unsigned int cksum;
};
struct extended_sigtable {
- unsigned int count;
- unsigned int cksum;
- unsigned int reserved[3];
+ unsigned int count;
+ unsigned int cksum;
+ unsigned int reserved[3];
struct extended_signature sigs[0];
};
typedef struct {
- unsigned long seg;
+ unsigned long seg;
} mm_segment_t;
@@ -541,7 +597,7 @@ extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
/* Free all resources held by a thread. */
extern void release_thread(struct task_struct *);
-/* Prepare to copy thread state - unlazy all lazy status */
+/* Prepare to copy thread state - unlazy all lazy state */
extern void prepare_to_copy(struct task_struct *tsk);
unsigned long get_wchan(struct task_struct *p);
@@ -578,118 +634,131 @@ static inline unsigned int cpuid_eax(unsigned int op)
unsigned int eax, ebx, ecx, edx;
cpuid(op, &eax, &ebx, &ecx, &edx);
+
return eax;
}
+
static inline unsigned int cpuid_ebx(unsigned int op)
{
unsigned int eax, ebx, ecx, edx;
cpuid(op, &eax, &ebx, &ecx, &edx);
+
return ebx;
}
+
static inline unsigned int cpuid_ecx(unsigned int op)
{
unsigned int eax, ebx, ecx, edx;
cpuid(op, &eax, &ebx, &ecx, &edx);
+
return ecx;
}
+
static inline unsigned int cpuid_edx(unsigned int op)
{
unsigned int eax, ebx, ecx, edx;
cpuid(op, &eax, &ebx, &ecx, &edx);
+
return edx;
}
/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
static inline void rep_nop(void)
{
- __asm__ __volatile__("rep;nop": : :"memory");
+ __asm__ __volatile__("rep; nop" ::: "memory");
}
-/* Stop speculative execution */
+static inline void cpu_relax(void)
+{
+ rep_nop();
+}
+
+/* Stop speculative execution: */
static inline void sync_core(void)
{
int tmp;
+
asm volatile("cpuid" : "=a" (tmp) : "0" (1)
: "ebx", "ecx", "edx", "memory");
}
-#define cpu_relax() rep_nop()
-
-static inline void __monitor(const void *eax, unsigned long ecx,
- unsigned long edx)
+static inline void
+__monitor(const void *eax, unsigned long ecx, unsigned long edx)
{
- /* "monitor %eax,%ecx,%edx;" */
+ /* "monitor %eax, %ecx, %edx;" */
asm volatile(
- ".byte 0x0f,0x01,0xc8;"
- : :"a" (eax), "c" (ecx), "d"(edx));
+ ".byte 0x0f, 0x01, 0xc8;"
+ :: "a" (eax), "c" (ecx), "d"(edx));
}
static inline void __mwait(unsigned long eax, unsigned long ecx)
{
- /* "mwait %eax,%ecx;" */
+ /* "mwait %eax, %ecx;" */
asm volatile(
- ".byte 0x0f,0x01,0xc9;"
- : :"a" (eax), "c" (ecx));
+ ".byte 0x0f, 0x01, 0xc9;"
+ :: "a" (eax), "c" (ecx));
}
static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
{
- /* "mwait %eax,%ecx;" */
+ /* "mwait %eax, %ecx;" */
asm volatile(
- "sti; .byte 0x0f,0x01,0xc9;"
- : :"a" (eax), "c" (ecx));
+ "sti; .byte 0x0f, 0x01, 0xc9;"
+ :: "a" (eax), "c" (ecx));
}
extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
-extern int force_mwait;
+extern int force_mwait;
extern void select_idle_routine(const struct cpuinfo_x86 *c);
-extern unsigned long boot_option_idle_override;
+extern unsigned long boot_option_idle_override;
extern void enable_sep_cpu(void);
extern int sysenter_setup(void);
/* Defined in head.S */
-extern struct desc_ptr early_gdt_descr;
+extern struct desc_ptr early_gdt_descr;
extern void cpu_set_gdt(int);
extern void switch_to_new_gdt(void);
extern void cpu_init(void);
extern void init_gdt(int cpu);
-/* from system description table in BIOS. Mostly for MCA use, but
- * others may find it useful. */
-extern unsigned int machine_id;
-extern unsigned int machine_submodel_id;
-extern unsigned int BIOS_revision;
+/*
+ * from system description table in BIOS. Mostly for MCA use, but
+ * others may find it useful:
+ */
+extern unsigned int machine_id;
+extern unsigned int machine_submodel_id;
+extern unsigned int BIOS_revision;
-/* Boot loader type from the setup header */
-extern int bootloader_type;
+/* Boot loader type from the setup header: */
+extern int bootloader_type;
-extern char ignore_fpu_irq;
-#define cache_line_size() (boot_cpu_data.x86_cache_alignment)
+extern char ignore_fpu_irq;
#define HAVE_ARCH_PICK_MMAP_LAYOUT 1
#define ARCH_HAS_PREFETCHW
#define ARCH_HAS_SPINLOCK_PREFETCH
#ifdef CONFIG_X86_32
-#define BASE_PREFETCH ASM_NOP4
-#define ARCH_HAS_PREFETCH
+# define BASE_PREFETCH ASM_NOP4
+# define ARCH_HAS_PREFETCH
#else
-#define BASE_PREFETCH "prefetcht0 (%1)"
+# define BASE_PREFETCH "prefetcht0 (%1)"
#endif
-/* Prefetch instructions for Pentium III and AMD Athlon */
-/* It's not worth to care about 3dnow! prefetches for the K6
- because they are microcoded there and very slow.
- However we don't do prefetches for pre XP Athlons currently
- That should be fixed. */
+/*
+ * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
+ *
+ * It's not worth to care about 3dnow prefetches for the K6
+ * because they are microcoded there and very slow.
+ */
static inline void prefetch(const void *x)
{
alternative_input(BASE_PREFETCH,
@@ -698,8 +767,11 @@ static inline void prefetch(const void *x)
"r" (x));
}
-/* 3dnow! prefetch to get an exclusive cache line. Useful for
- spinlocks to avoid one state transition in the cache coherency protocol. */
+/*
+ * 3dnow prefetch to get an exclusive cache line.
+ * Useful for spinlocks to avoid one state transition in the
+ * cache coherency protocol:
+ */
static inline void prefetchw(const void *x)
{
alternative_input(BASE_PREFETCH,
@@ -708,21 +780,25 @@ static inline void prefetchw(const void *x)
"r" (x));
}
-#define spin_lock_prefetch(x) prefetchw(x)
+static inline void spin_lock_prefetch(const void *x)
+{
+ prefetchw(x);
+}
+
#ifdef CONFIG_X86_32
/*
* User space process size: 3GB (default).
*/
-#define TASK_SIZE (PAGE_OFFSET)
-#define STACK_TOP TASK_SIZE
-#define STACK_TOP_MAX STACK_TOP
-
-#define INIT_THREAD { \
- .sp0 = sizeof(init_stack) + (long)&init_stack, \
- .vm86_info = NULL, \
- .sysenter_cs = __KERNEL_CS, \
- .io_bitmap_ptr = NULL, \
- .fs = __KERNEL_PERCPU, \
+#define TASK_SIZE PAGE_OFFSET
+#define STACK_TOP TASK_SIZE
+#define STACK_TOP_MAX STACK_TOP
+
+#define INIT_THREAD { \
+ .sp0 = sizeof(init_stack) + (long)&init_stack, \
+ .vm86_info = NULL, \
+ .sysenter_cs = __KERNEL_CS, \
+ .io_bitmap_ptr = NULL, \
+ .fs = __KERNEL_PERCPU, \
}
/*
@@ -731,26 +807,27 @@ static inline void prefetchw(const void *x)
* permission bitmap. The extra byte must be all 1 bits, and must
* be within the limit.
*/
-#define INIT_TSS { \
- .x86_tss = { \
+#define INIT_TSS { \
+ .x86_tss = { \
.sp0 = sizeof(init_stack) + (long)&init_stack, \
- .ss0 = __KERNEL_DS, \
- .ss1 = __KERNEL_CS, \
- .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
- }, \
- .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
+ .ss0 = __KERNEL_DS, \
+ .ss1 = __KERNEL_CS, \
+ .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
+ }, \
+ .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
}
-#define start_thread(regs, new_eip, new_esp) do { \
+#define start_thread(regs, new_eip, new_esp) \
+do { \
__asm__("movl %0,%%gs": :"r" (0)); \
- regs->fs = 0; \
+ regs->fs = 0; \
set_fs(USER_DS); \
- regs->ds = __USER_DS; \
- regs->es = __USER_DS; \
- regs->ss = __USER_DS; \
- regs->cs = __USER_CS; \
- regs->ip = new_eip; \
- regs->sp = new_esp; \
+ regs->ds = __USER_DS; \
+ regs->es = __USER_DS; \
+ regs->ss = __USER_DS; \
+ regs->cs = __USER_CS; \
+ regs->ip = new_eip; \
+ regs->sp = new_esp; \
} while (0)
@@ -780,24 +857,24 @@ extern unsigned long thread_saved_pc(struct task_struct *tsk);
__regs__ - 1; \
})
-#define KSTK_ESP(task) (task_pt_regs(task)->sp)
+#define KSTK_ESP(task) (task_pt_regs(task)->sp)
#else
/*
* User space process size. 47bits minus one guard page.
*/
-#define TASK_SIZE64 (0x800000000000UL - 4096)
+#define TASK_SIZE64 (0x800000000000UL - 4096)
/* This decides where the kernel will search for a free chunk of vm
* space during mmap's.
*/
-#define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
- 0xc0000000 : 0xFFFFe000)
+#define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
+ 0xc0000000 : 0xFFFFe000)
-#define TASK_SIZE (test_thread_flag(TIF_IA32) ? \
- IA32_PAGE_OFFSET : TASK_SIZE64)
-#define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \
- IA32_PAGE_OFFSET : TASK_SIZE64)
+#define TASK_SIZE (test_thread_flag(TIF_IA32) ? \
+ IA32_PAGE_OFFSET : TASK_SIZE64)
+#define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \
+ IA32_PAGE_OFFSET : TASK_SIZE64)
#define STACK_TOP TASK_SIZE
#define STACK_TOP_MAX TASK_SIZE64
@@ -813,12 +890,12 @@ extern unsigned long thread_saved_pc(struct task_struct *tsk);
#define start_thread(regs, new_rip, new_rsp) do { \
asm volatile("movl %0,%%fs; movl %0,%%es; movl %0,%%ds": :"r" (0)); \
load_gs_index(0); \
- (regs)->ip = (new_rip); \
- (regs)->sp = (new_rsp); \
+ (regs)->ip = (new_rip); \
+ (regs)->sp = (new_rsp); \
write_pda(oldrsp, (new_rsp)); \
- (regs)->cs = __USER_CS; \
- (regs)->ss = __USER_DS; \
- (regs)->flags = 0x200; \
+ (regs)->cs = __USER_CS; \
+ (regs)->ss = __USER_DS; \
+ (regs)->flags = 0x200; \
set_fs(USER_DS); \
} while (0)
@@ -826,17 +903,18 @@ extern unsigned long thread_saved_pc(struct task_struct *tsk);
* Return saved PC of a blocked thread.
* What is this good for? it will be always the scheduler or ret_from_fork.
*/
-#define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
+#define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
-#define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
-#define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */
+#define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
+#define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */
#endif /* CONFIG_X86_64 */
-/* This decides where the kernel will search for a free chunk of vm
+/*
+ * This decides where the kernel will search for a free chunk of vm
* space during mmap's.
*/
#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
-#define KSTK_EIP(task) (task_pt_regs(task)->ip)
+#define KSTK_EIP(task) (task_pt_regs(task)->ip)
#endif
commit edc05e6de3e2fd203da21ba984b19d92e5398b62
Author: Ingo Molnar <mingo@elte.hu>
Date: Mon Feb 18 03:30:47 2008 +0100
x86: more coding style fixes in centaur.c
no code changed:
arch/x86/kernel/cpu/centaur.o:
text data bss dec hex filename
1031 324 0 1355 54b centaur.o.before
1031 324 0 1355 54b centaur.o.after
md5:
4f306a7f980b58eb69c4bdcfcde565f1 centaur.o.before.asm
4f306a7f980b58eb69c4bdcfcde565f1 centaur.o.after.asm
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index 710fe1ed0731..efe8da88da53 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -1,10 +1,12 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/bitops.h>
+
#include <asm/processor.h>
#include <asm/msr.h>
#include <asm/e820.h>
#include <asm/mtrr.h>
+
#include "cpu.h"
#ifdef CONFIG_X86_OOSTORE
@@ -12,16 +14,17 @@
static u32 __cpuinit power2(u32 x)
{
u32 s = 1;
- while(s <= x)
+
+ while (s <= x)
s <<= 1;
+
return s >>= 1;
}
/*
- * Set up an actual MCR
+ * Set up an actual MCR
*/
-
static void __cpuinit centaur_mcr_insert(int reg, u32 base, u32 size, int key)
{
u32 lo, hi;
@@ -35,16 +38,15 @@ static void __cpuinit centaur_mcr_insert(int reg, u32 base, u32 size, int key)
}
/*
- * Figure what we can cover with MCR's
+ * Figure what we can cover with MCR's
*
- * Shortcut: We know you can't put 4Gig of RAM on a winchip
+ * Shortcut: We know you can't put 4Gig of RAM on a winchip
*/
-
-static u32 __cpuinit ramtop(void) /* 16388 */
+static u32 __cpuinit ramtop(void)
{
- int i;
- u32 top = 0;
u32 clip = 0xFFFFFFFFUL;
+ u32 top = 0;
+ int i;
for (i = 0; i < e820.nr_map; i++) {
unsigned long start, end;
@@ -52,13 +54,12 @@ static u32 __cpuinit ramtop(void) /* 16388 */
if (e820.map[i].addr > 0xFFFFFFFFUL)
continue;
/*
- * Don't MCR over reserved space. Ignore the ISA hole
- * we frob around that catastrophe already
+ * Don't MCR over reserved space. Ignore the ISA hole
+ * we frob around that catastrophe already
*/
-
- if (e820.map[i].type == E820_RESERVED)
- {
- if (e820.map[i].addr >= 0x100000UL && e820.map[i].addr < clip)
+ if (e820.map[i].type == E820_RESERVED) {
+ if (e820.map[i].addr >= 0x100000UL &&
+ e820.map[i].addr < clip)
clip = e820.map[i].addr;
continue;
}
@@ -69,28 +70,27 @@ static u32 __cpuinit ramtop(void) /* 16388 */
if (end > top)
top = end;
}
- /* Everything below 'top' should be RAM except for the ISA hole.
- Because of the limited MCR's we want to map NV/ACPI into our
- MCR range for gunk in RAM
-
- Clip might cause us to MCR insufficient RAM but that is an
- acceptable failure mode and should only bite obscure boxes with
- a VESA hole at 15Mb
-
- The second case Clip sometimes kicks in is when the EBDA is marked
- as reserved. Again we fail safe with reasonable results
- */
-
- if(top > clip)
+ /*
+ * Everything below 'top' should be RAM except for the ISA hole.
+ * Because of the limited MCR's we want to map NV/ACPI into our
+ * MCR range for gunk in RAM
+ *
+ * Clip might cause us to MCR insufficient RAM but that is an
+ * acceptable failure mode and should only bite obscure boxes with
+ * a VESA hole at 15Mb
+ *
+ * The second case Clip sometimes kicks in is when the EBDA is marked
+ * as reserved. Again we fail safe with reasonable results
+ */
+ if (top > clip)
top = clip;
return top;
}
/*
- * Compute a set of MCR's to give maximum coverage
+ * Compute a set of MCR's to give maximum coverage
*/
-
static int __cpuinit centaur_mcr_compute(int nr, int key)
{
u32 mem = ramtop();
@@ -100,33 +100,31 @@ static int __cpuinit centaur_mcr_compute(int nr, int key)
u32 floor = 0;
int ct = 0;
- while (ct < nr)
- {
+ while (ct < nr) {
u32 fspace = 0;
+ u32 high;
+ u32 low;
/*
- * Find the largest block we will fill going upwards
+ * Find the largest block we will fill going upwards
*/
-
- u32 high = power2(mem-top);
+ high = power2(mem-top);
/*
- * Find the largest block we will fill going downwards
+ * Find the largest block we will fill going downwards
*/
-
- u32 low = base/2;
+ low = base/2;
/*
- * Don't fill below 1Mb going downwards as there
- * is an ISA hole in the way.
+ * Don't fill below 1Mb going downwards as there
+ * is an ISA hole in the way.
*/
-
if (base <= 1024*1024)
low = 0;
/*
- * See how much space we could cover by filling below
- * the ISA hole
+ * See how much space we could cover by filling below
+ * the ISA hole
*/
if (floor == 0)
@@ -137,52 +135,48 @@ static int __cpuinit centaur_mcr_compute(int nr, int key)
/* And forget ROM space */
/*
- * Now install the largest coverage we get
+ * Now install the largest coverage we get
*/
-
- if (fspace > high && fspace > low)
- {
+ if (fspace > high && fspace > low) {
centaur_mcr_insert(ct, floor, fspace, key);
floor += fspace;
- }
- else if (high > low) {
+ } else if (high > low) {
centaur_mcr_insert(ct, top, high, key);
top += high;
- }
- else if (low > 0) {
+ } else if (low > 0) {
base -= low;
centaur_mcr_insert(ct, base, low, key);
- }
- else break;
+ } else
+ break;
ct++;
}
/*
- * We loaded ct values. We now need to set the mask. The caller
- * must do this bit.
+ * We loaded ct values. We now need to set the mask. The caller
+ * must do this bit.
*/
-
return ct;
}
static void __cpuinit centaur_create_optimal_mcr(void)
{
+ int used;
int i;
+
/*
- * Allocate up to 6 mcrs to mark as much of ram as possible
- * as write combining and weak write ordered.
+ * Allocate up to 6 mcrs to mark as much of ram as possible
+ * as write combining and weak write ordered.
*
- * To experiment with: Linux never uses stack operations for
- * mmio spaces so we could globally enable stack operation wc
+ * To experiment with: Linux never uses stack operations for
+ * mmio spaces so we could globally enable stack operation wc
*
- * Load the registers with type 31 - full write combining, all
- * writes weakly ordered.
+ * Load the registers with type 31 - full write combining, all
+ * writes weakly ordered.
*/
- int used = centaur_mcr_compute(6, 31);
+ used = centaur_mcr_compute(6, 31);
/*
- * Wipe unused MCRs
+ * Wipe unused MCRs
*/
-
for (i = used; i < 8; i++)
wrmsr(MSR_IDT_MCR0+i, 0, 0);
}
@@ -190,31 +184,30 @@ static void __cpuinit centaur_create_optimal_mcr(void)
static void __cpuinit winchip2_create_optimal_mcr(void)
{
u32 lo, hi;
+ int used;
int i;
/*
- * Allocate up to 6 mcrs to mark as much of ram as possible
- * as write combining, weak store ordered.
+ * Allocate up to 6 mcrs to mark as much of ram as possible
+ * as write combining, weak store ordered.
*
- * Load the registers with type 25
- * 8 - weak write ordering
- * 16 - weak read ordering
- * 1 - write combining
+ * Load the registers with type 25
+ * 8 - weak write ordering
+ * 16 - weak read ordering
+ * 1 - write combining
*/
-
- int used = centaur_mcr_compute(6, 25);
+ used = centaur_mcr_compute(6, 25);
/*
- * Mark the registers we are using.
+ * Mark the registers we are using.
*/
-
rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
for (i = 0; i < used; i++)
lo |= 1<<(9+i);
wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
/*
- * Wipe unused MCRs
+ * Wipe unused MCRs
*/
for (i = used; i < 8; i++)
@@ -222,9 +215,8 @@ static void __cpuinit winchip2_create_optimal_mcr(void)
}
/*
- * Handle the MCR key on the Winchip 2.
+ * Handle the MCR key on the Winchip 2.
*/
-
static void __cpuinit winchip2_unprotect_mcr(void)
{
u32 lo, hi;
@@ -301,28 +293,29 @@ static void __cpuinit init_c3(struct cpuinfo_x86 *c)
display_cacheinfo(c);
}
+enum {
+ ECX8 = 1<<1,
+ EIERRINT = 1<<2,
+ DPM = 1<<3,
+ DMCE = 1<<4,
+ DSTPCLK = 1<<5,
+ ELINEAR = 1<<6,
+ DSMC = 1<<7,
+ DTLOCK = 1<<8,
+ EDCTLB = 1<<8,
+ EMMX = 1<<9,
+ DPDC = 1<<11,
+ EBRPRED = 1<<12,
+ DIC = 1<<13,
+ DDC = 1<<14,
+ DNA = 1<<15,
+ ERETSTK = 1<<16,
+ E2MMX = 1<<19,
+ EAMD3D = 1<<20,
+};
+
static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
{
- enum {
- ECX8 = 1<<1,
- EIERRINT = 1<<2,
- DPM = 1<<3,
- DMCE = 1<<4,
- DSTPCLK = 1<<5,
- ELINEAR = 1<<6,
- DSMC = 1<<7,
- DTLOCK = 1<<8,
- EDCTLB = 1<<8,
- EMMX = 1<<9,
- DPDC = 1<<11,
- EBRPRED = 1<<12,
- DIC = 1<<13,
- DDC = 1<<14,
- DNA = 1<<15,
- ERETSTK = 1<<16,
- E2MMX = 1<<19,
- EAMD3D = 1<<20,
- };
char *name;
u32 fcr_set = 0;
@@ -330,126 +323,137 @@ static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
u32 lo, hi, newlo;
u32 aa, bb, cc, dd;
- /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
- 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
+ /*
+ * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
+ * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
+ */
clear_bit(0*32+31, c->x86_capability);
switch (c->x86) {
-
case 5:
- switch (c->x86_model) {
- case 4:
- name = "C6";
- fcr_set = ECX8|DSMC|EDCTLB|EMMX|ERETSTK;
- fcr_clr = DPDC;
- printk(KERN_NOTICE "Disabling bugged TSC.\n");
- clear_bit(X86_FEATURE_TSC, c->x86_capability);
+ switch (c->x86_model) {
+ case 4:
+ name = "C6";
+ fcr_set = ECX8|DSMC|EDCTLB|EMMX|ERETSTK;
+ fcr_clr = DPDC;
+ printk(KERN_NOTICE "Disabling bugged TSC.\n");
+ clear_bit(X86_FEATURE_TSC, c->x86_capability);
#ifdef CONFIG_X86_OOSTORE
- centaur_create_optimal_mcr();
- /* Enable
- write combining on non-stack, non-string
- write combining on string, all types
- weak write ordering
-
- The C6 original lacks weak read order
-
- Note 0x120 is write only on Winchip 1 */
-
- wrmsr(MSR_IDT_MCR_CTRL, 0x01F0001F, 0);
+ centaur_create_optimal_mcr();
+ /*
+ * Enable:
+ * write combining on non-stack, non-string
+ * write combining on string, all types
+ * weak write ordering
+ *
+ * The C6 original lacks weak read order
+ *
+ * Note 0x120 is write only on Winchip 1
+ */
+ wrmsr(MSR_IDT_MCR_CTRL, 0x01F0001F, 0);
#endif
+ break;
+ case 8:
+ switch (c->x86_mask) {
+ default:
+ name = "2";
break;
- case 8:
- switch (c->x86_mask) {
- default:
- name = "2";
- break;
- case 7 ... 9:
- name = "2A";
- break;
- case 10 ... 15:
- name = "2B";
- break;
- }
- fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|E2MMX|EAMD3D;
- fcr_clr = DPDC;
+ case 7 ... 9:
+ name = "2A";
+ break;
+ case 10 ... 15:
+ name = "2B";
+ break;
+ }
+ fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
+ E2MMX|EAMD3D;
+ fcr_clr = DPDC;
#ifdef CONFIG_X86_OOSTORE
- winchip2_unprotect_mcr();
- winchip2_create_optimal_mcr();
- rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
- /* Enable
- write combining on non-stack, non-string
- write combining on string, all types
- weak write ordering
- */
- lo |= 31;
- wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
- winchip2_protect_mcr();
+ winchip2_unprotect_mcr();
+ winchip2_create_optimal_mcr();
+ rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
+ /*
+ * Enable:
+ * write combining on non-stack, non-string
+ * write combining on string, all types
+ * weak write ordering
+ */
+ lo |= 31;
+ wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
+ winchip2_protect_mcr();
#endif
- break;
- case 9:
- name = "3";
- fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|E2MMX|EAMD3D;
- fcr_clr = DPDC;
+ break;
+ case 9:
+ name = "3";
+ fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
+ E2MMX|EAMD3D;
+ fcr_clr = DPDC;
#ifdef CONFIG_X86_OOSTORE
- winchip2_unprotect_mcr();
- winchip2_create_optimal_mcr();
- rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
- /* Enable
- write combining on non-stack, non-string
- write combining on string, all types
- weak write ordering
- */
- lo |= 31;
- wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
- winchip2_protect_mcr();
+ winchip2_unprotect_mcr();
+ winchip2_create_optimal_mcr();
+ rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
+ /*
+ * Enable:
+ * write combining on non-stack, non-string
+ * write combining on string, all types
+ * weak write ordering
+ */
+ lo |= 31;
+ wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
+ winchip2_protect_mcr();
#endif
- break;
- default:
- name = "??";
- }
+ break;
+ default:
+ name = "??";
+ }
- rdmsr(MSR_IDT_FCR1, lo, hi);
- newlo = (lo|fcr_set) & (~fcr_clr);
+ rdmsr(MSR_IDT_FCR1, lo, hi);
+ newlo = (lo|fcr_set) & (~fcr_clr);
- if (newlo != lo) {
- printk(KERN_INFO "Centaur FCR was 0x%X now 0x%X\n", lo, newlo);
- wrmsr(MSR_IDT_FCR1, newlo, hi);
- } else {
- printk(KERN_INFO "Centaur FCR is 0x%X\n", lo);
- }
- /* Emulate MTRRs using Centaur's MCR. */
- set_bit(X86_FEATURE_CENTAUR_MCR, c->x86_capability);
- /* Report CX8 */
- set_bit(X86_FEATURE_CX8, c->x86_capability);
- /* Set 3DNow! on Winchip 2 and above. */
- if (c->x86_model >= 8)
- set_bit(X86_FEATURE_3DNOW, c->x86_capability);
- /* See if we can find out some more. */
- if (cpuid_eax(0x80000000) >= 0x80000005) {
- /* Yes, we can. */
- cpuid(0x80000005, &aa, &bb, &cc, &dd);
- /* Add L1 data and code cache sizes. */
- c->x86_cache_size = (cc>>24)+(dd>>24);
- }
- sprintf(c->x86_model_id, "WinChip %s", name);
- break;
+ if (newlo != lo) {
+ printk(KERN_INFO "Centaur FCR was 0x%X now 0x%X\n",
+ lo, newlo);
+ wrmsr(MSR_IDT_FCR1, newlo, hi);
+ } else {
+ printk(KERN_INFO "Centaur FCR is 0x%X\n", lo);
+ }
+ /* Emulate MTRRs using Centaur's MCR. */
+ set_bit(X86_FEATURE_CENTAUR_MCR, c->x86_capability);
+ /* Report CX8 */
+ set_bit(X86_FEATURE_CX8, c->x86_capability);
+ /* Set 3DNow! on Winchip 2 and above. */
+ if (c->x86_model >= 8)
+ set_bit(X86_FEATURE_3DNOW, c->x86_capability);
+ /* See if we can find out some more. */
+ if (cpuid_eax(0x80000000) >= 0x80000005) {
+ /* Yes, we can. */
+ cpuid(0x80000005, &aa, &bb, &cc, &dd);
+ /* Add L1 data and code cache sizes. */
+ c->x86_cache_size = (cc>>24)+(dd>>24);
+ }
+ sprintf(c->x86_model_id, "WinChip %s", name);
+ break;
case 6:
- init_c3(c);
- break;
+ init_c3(c);
+ break;
}
}
-static unsigned int __cpuinit centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size)
+static unsigned int __cpuinit
+centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size)
{
/* VIA C3 CPUs (670-68F) need further shifting. */
if ((c->x86 == 6) && ((c->x86_model == 7) || (c->x86_model == 8)))
size >>= 8;
- /* VIA also screwed up Nehemiah stepping 1, and made
- it return '65KB' instead of '64KB'
- - Note, it seems this may only be in engineering samples. */
- if ((c->x86 == 6) && (c->x86_model == 9) && (c->x86_mask == 1) && (size == 65))
+ /*
+ * There's also an erratum in Nehemiah stepping 1, which
+ * returns '65KB' instead of '64KB'
+ * - Note, it seems this may only be in engineering samples.
+ */
+ if ((c->x86 == 6) && (c->x86_model == 9) &&
+ (c->x86_mask == 1) && (size == 65))
size -= 1;
return size;
commit ca5d3f14915f5f8db75f7b0c198c0c154947fc5e
Author: Ingo Molnar <mingo@elte.hu>
Date: Mon Feb 18 08:53:56 2008 +0100
x86: clean up mmx_32.c
checkpatch.pl --file cleanups:
before:
total: 74 errors, 3 warnings, 386 lines checked
after:
total: 0 errors, 0 warnings, 377 lines checked
no code changed:
arch/x86/lib/mmx_32.o:
text data bss dec hex filename
1323 0 8 1331 533 mmx_32.o.before
1323 0 8 1331 533 mmx_32.o.after
md5:
4cc39f1017dc40a5ebf02ce0ff7312bc mmx_32.o.before.asm
4cc39f1017dc40a5ebf02ce0ff7312bc mmx_32.o.after.asm
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
diff --git a/arch/x86/lib/mmx_32.c b/arch/x86/lib/mmx_32.c
index cc9b4a4450f3..c9f2d9ba8dd8 100644
--- a/arch/x86/lib/mmx_32.c
+++ b/arch/x86/lib/mmx_32.c
@@ -1,32 +1,30 @@
-#include <linux/types.h>
-#include <linux/string.h>
-#include <linux/sched.h>
-#include <linux/hardirq.h>
-#include <linux/module.h>
-
-#include <asm/asm.h>
-#include <asm/i387.h>
-
-
/*
* MMX 3DNow! library helper functions
*
* To do:
- * We can use MMX just for prefetch in IRQ's. This may be a win.
+ * We can use MMX just for prefetch in IRQ's. This may be a win.
* (reported so on K6-III)
* We should use a better code neutral filler for the short jump
* leal ebx. [ebx] is apparently best for K6-2, but Cyrix ??
* We also want to clobber the filler register so we don't get any
- * register forwarding stalls on the filler.
+ * register forwarding stalls on the filler.
*
* Add *user handling. Checksums are not a win with MMX on any CPU
* tested so far for any MMX solution figured.
*
- * 22/09/2000 - Arjan van de Ven
- * Improved for non-egineering-sample Athlons
+ * 22/09/2000 - Arjan van de Ven
+ * Improved for non-egineering-sample Athlons
*
*/
-
+#include <linux/hardirq.h>
+#include <linux/string.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/types.h>
+
+#include <asm/i387.h>
+#include <asm/asm.h>
+
void *_mmx_memcpy(void *to, const void *from, size_t len)
{
void *p;
@@ -51,12 +49,10 @@ void *_mmx_memcpy(void *to, const void *from, size_t len)
"3: movw $0x1AEB, 1b\n" /* jmp on 26 bytes */
" jmp 2b\n"
".previous\n"
- _ASM_EXTABLE(1b,3b)
- : : "r" (from) );
-
-
- for(; i>5; i--)
- {
+ _ASM_EXTABLE(1b, 3b)
+ : : "r" (from));
+
+ for ( ; i > 5; i--) {
__asm__ __volatile__ (
"1: prefetch 320(%0)\n"
"2: movq (%0), %%mm0\n"
@@ -79,14 +75,14 @@ void *_mmx_memcpy(void *to, const void *from, size_t len)
"3: movw $0x05EB, 1b\n" /* jmp on 5 bytes */
" jmp 2b\n"
".previous\n"
- _ASM_EXTABLE(1b,3b)
- : : "r" (from), "r" (to) : "memory");
- from+=64;
- to+=64;
+ _ASM_EXTABLE(1b, 3b)
+ : : "r" (from), "r" (to) : "memory");
+
+ from += 64;
+ to += 64;
}
- for(; i>0; i--)
- {
+ for ( ; i > 0; i--) {
__asm__ __volatile__ (
" movq (%0), %%mm0\n"
" movq 8(%0), %%mm1\n"
@@ -104,17 +100,20 @@ void *_mmx_memcpy(void *to, const void *from, size_t len)
" movq %%mm1, 40(%1)\n"
" movq %%mm2, 48(%1)\n"
" movq %%mm3, 56(%1)\n"
- : : "r" (from), "r" (to) : "memory");
- from+=64;
- to+=64;
+ : : "r" (from), "r" (to) : "memory");
+
+ from += 64;
+ to += 64;
}
/*
- * Now do the tail of the block
+ * Now do the tail of the block:
*/
- __memcpy(to, from, len&63);
+ __memcpy(to, from, len & 63);
kernel_fpu_end();
+
return p;
}
+EXPORT_SYMBOL(_mmx_memcpy);
#ifdef CONFIG_MK7
@@ -128,13 +127,12 @@ static void fast_clear_page(void *page)
int i;
kernel_fpu_begin();
-
+
__asm__ __volatile__ (
" pxor %%mm0, %%mm0\n" : :
);
- for(i=0;i<4096/64;i++)
- {
+ for (i = 0; i < 4096/64; i++) {
__asm__ __volatile__ (
" movntq %%mm0, (%0)\n"
" movntq %%mm0, 8(%0)\n"
@@ -145,14 +143,15 @@ static void fast_clear_page(void *page)
" movntq %%mm0, 48(%0)\n"
" movntq %%mm0, 56(%0)\n"
: : "r" (page) : "memory");
- page+=64;
+ page += 64;
}
- /* since movntq is weakly-ordered, a "sfence" is needed to become
- * ordered again.
+
+ /*
+ * Since movntq is weakly-ordered, a "sfence" is needed to become
+ * ordered again:
*/
- __asm__ __volatile__ (
- " sfence \n" : :
- );
+ __asm__ __volatile__("sfence\n"::);
+
kernel_fpu_end();
}
@@ -162,10 +161,11 @@ static void fast_copy_page(void *to, void *from)
kernel_fpu_begin();
- /* maybe the prefetch stuff can go before the expensive fnsave...
+ /*
+ * maybe the prefetch stuff can go before the expensive fnsave...
* but that is for later. -AV
*/
- __asm__ __volatile__ (
+ __asm__ __volatile__(
"1: prefetch (%0)\n"
" prefetch 64(%0)\n"
" prefetch 128(%0)\n"
@@ -176,11 +176,9 @@ static void fast_copy_page(void *to, void *from)
"3: movw $0x1AEB, 1b\n" /* jmp on 26 bytes */
" jmp 2b\n"
".previous\n"
- _ASM_EXTABLE(1b,3b)
- : : "r" (from) );
+ _ASM_EXTABLE(1b, 3b) : : "r" (from));
- for(i=0; i<(4096-320)/64; i++)
- {
+ for (i = 0; i < (4096-320)/64; i++) {
__asm__ __volatile__ (
"1: prefetch 320(%0)\n"
"2: movq (%0), %%mm0\n"
@@ -203,13 +201,13 @@ static void fast_copy_page(void *to, void *from)
"3: movw $0x05EB, 1b\n" /* jmp on 5 bytes */
" jmp 2b\n"
".previous\n"
- _ASM_EXTABLE(1b,3b)
- : : "r" (from), "r" (to) : "memory");
- from+=64;
- to+=64;
+ _ASM_EXTABLE(1b, 3b) : : "r" (from), "r" (to) : "memory");
+
+ from += 64;
+ to += 64;
}
- for(i=(4096-320)/64; i<4096/64; i++)
- {
+
+ for (i = (4096-320)/64; i < 4096/64; i++) {
__asm__ __volatile__ (
"2: movq (%0), %%mm0\n"
" movntq %%mm0, (%1)\n"
@@ -227,37 +225,34 @@ static void fast_copy_page(void *to, void *from)
" movntq %%mm6, 48(%1)\n"
" movq 56(%0), %%mm7\n"
" movntq %%mm7, 56(%1)\n"
- : : "r" (from), "r" (to) : "memory");
- from+=64;
- to+=64;
+ : : "r" (from), "r" (to) : "memory");
+ from += 64;
+ to += 64;
}
- /* since movntq is weakly-ordered, a "sfence" is needed to become
- * ordered again.
+ /*
+ * Since movntq is weakly-ordered, a "sfence" is needed to become
+ * ordered again:
*/
- __asm__ __volatile__ (
- " sfence \n" : :
- );
+ __asm__ __volatile__("sfence \n"::);
kernel_fpu_end();
}
-#else
+#else /* CONFIG_MK7 */
/*
* Generic MMX implementation without K7 specific streaming
*/
-
static void fast_clear_page(void *page)
{
int i;
-
+
kernel_fpu_begin();
-
+
__asm__ __volatile__ (
" pxor %%mm0, %%mm0\n" : :
);
- for(i=0;i<4096/128;i++)
- {
+ for (i = 0; i < 4096/128; i++) {
__asm__ __volatile__ (
" movq %%mm0, (%0)\n"
" movq %%mm0, 8(%0)\n"
@@ -275,8 +270,8 @@ static void fast_clear_page(void *page)
" movq %%mm0, 104(%0)\n"
" movq %%mm0, 112(%0)\n"
" movq %%mm0, 120(%0)\n"
- : : "r" (page) : "memory");
- page+=128;
+ : : "r" (page) : "memory");
+ page += 128;
}
kernel_fpu_end();
@@ -285,8 +280,7 @@ static void fast_clear_page(void *page)
static void fast_copy_page(void *to, void *from)
{
int i;
-
-
+
kernel_fpu_begin();
__asm__ __volatile__ (
@@ -300,11 +294,9 @@ static void fast_copy_page(void *to, void *from)
"3: movw $0x1AEB, 1b\n" /* jmp on 26 bytes */
" jmp 2b\n"
".previous\n"
- _ASM_EXTABLE(1b,3b)
- : : "r" (from) );
+ _ASM_EXTABLE(1b, 3b) : : "r" (from));
- for(i=0; i<4096/64; i++)
- {
+ for (i = 0; i < 4096/64; i++) {
__asm__ __volatile__ (
"1: prefetch 320(%0)\n"
"2: movq (%0), %%mm0\n"
@@ -327,60 +319,59 @@ static void fast_copy_page(void *to, void *from)
"3: movw $0x05EB, 1b\n" /* jmp on 5 bytes */
" jmp 2b\n"
".previous\n"
- _ASM_EXTABLE(1b,3b)
- : : "r" (from), "r" (to) : "memory");
- from+=64;
- to+=64;
+ _ASM_EXTABLE(1b, 3b)
+ : : "r" (from), "r" (to) : "memory");
+
+ from += 64;
+ to += 64;
}
kernel_fpu_end();
}
-
-#endif
+#endif /* !CONFIG_MK7 */
/*
- * Favour MMX for page clear and copy.
+ * Favour MMX for page clear and copy:
*/
-
-static void slow_zero_page(void * page)
+static void slow_zero_page(void *page)
{
int d0, d1;
- __asm__ __volatile__( \
- "cld\n\t" \
- "rep ; stosl" \
- : "=&c" (d0), "=&D" (d1)
- :"a" (0),"1" (page),"0" (1024)
- :"memory");
+
+ __asm__ __volatile__(
+ "cld\n\t"
+ "rep ; stosl"
+
+ : "=&c" (d0), "=&D" (d1)
+ :"a" (0), "1" (page), "0" (1024)
+ :"memory");
}
-
-void mmx_clear_page(void * page)
+
+void mmx_clear_page(void *page)
{
- if(unlikely(in_interrupt()))
+ if (unlikely(in_interrupt()))
slow_zero_page(page);
else
fast_clear_page(page);
}
+EXPORT_SYMBOL(mmx_clear_page);
static void slow_copy_page(void *to, void *from)
{
int d0, d1, d2;
- __asm__ __volatile__( \
- "cld\n\t" \
- "rep ; movsl" \
- : "=&c" (d0), "=&D" (d1), "=&S" (d2) \
- : "0" (1024),"1" ((long) to),"2" ((long) from) \
+
+ __asm__ __volatile__(
+ "cld\n\t"
+ "rep ; movsl"
+ : "=&c" (d0), "=&D" (d1), "=&S" (d2)
+ : "0" (1024), "1" ((long) to), "2" ((long) from)
: "memory");
}
-
void mmx_copy_page(void *to, void *from)
{
- if(unlikely(in_interrupt()))
+ if (unlikely(in_interrupt()))
slow_copy_page(to, from);
else
fast_copy_page(to, from);
}
-
-EXPORT_SYMBOL(_mmx_memcpy);
-EXPORT_SYMBOL(mmx_clear_page);
EXPORT_SYMBOL(mmx_copy_page);
commit 52b387197beb5c89f734f057553fdf7d417b448c
Author: Ingo Molnar <mingo@elte.hu>
Date: Sun Feb 17 20:06:36 2008 +0100
x86: bump image header to version 2.08.
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
diff --git a/arch/x86/boot/header.S b/arch/x86/boot/header.S
index 8471658d5534..40c91bb483e1 100644
--- a/arch/x86/boot/header.S
+++ b/arch/x86/boot/header.S
@@ -120,7 +120,7 @@ _start:
# Part 2 of the header, from the old setup.S
.ascii "HdrS" # header signature
- .word 0x0207 # header version number (>= 0x0105)
+ .word 0x0208 # header version number (>= 0x0105)
# or else old loadlin-1.5 will fail)
.globl realmode_swtch
realmode_swtch: .word 0, 0 # default_switch, SETUPSEG