Patches contributed by Eötvös Lorand University
commit 6ce37a58e334ef773f88283939afc9f4965c7697
Merge: d7ba11d01cfe 91467bdf6e53
Author: Ingo Molnar <mingo@elte.hu>
Date: Mon Jul 28 17:19:02 2008 +0200
Merge branch 'x86/crashdump' into x86/urgent
commit 71998e83c520c7a91b254dc9705baeedbee0d44f
Merge: c9272c4f9fbe 99bbc4b1e677
Author: Ingo Molnar <mingo@elte.hu>
Date: Mon Jul 28 17:03:43 2008 +0200
Merge branch 'x86-tracehook' of git://git.kernel.org/pub/scm/linux/kernel/git/frob/linux-2.6-utrace into x86/tracehook
commit 239bd83104ec6bcba90221d8b0973d2565142ef8
Author: Ingo Molnar <mingo@elte.hu>
Date: Mon Jul 28 16:45:49 2008 +0200
x86: L3 cache index disable for 2.6.26, fix #2
fix !PCI build failure:
arch/x86/kernel/cpu/intel_cacheinfo.c: In function 'get_k8_northbridge':
arch/x86/kernel/cpu/intel_cacheinfo.c:675: error: implicit declaration of function 'pci_match_id'
Signed-off-by: Ingo Molnar <mingo@elte.hu>
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index d763d24187c2..1677b55371a5 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -135,11 +135,13 @@ struct _cpuid4_info {
cpumask_t shared_cpu_map; /* future?: only cpus/node is needed */
};
+#ifdef CONFIG_PCI
static struct pci_device_id k8_nb_id[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1103) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1203) },
{}
};
+#endif
unsigned short num_cache_leaves;
@@ -663,6 +665,7 @@ static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf) {
#define to_object(k) container_of(k, struct _index_kobject, kobj)
#define to_attr(a) container_of(a, struct _cache_attr, attr)
+#ifdef CONFIG_PCI
static struct pci_dev *get_k8_northbridge(int node)
{
struct pci_dev *dev = NULL;
@@ -679,6 +682,12 @@ static struct pci_dev *get_k8_northbridge(int node)
}
return dev;
}
+#else
+static struct pci_dev *get_k8_northbridge(int node)
+{
+ return NULL;
+}
+#endif
static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf)
{
commit b7d0b6784565b846f3562608dfb3cf8516718724
Merge: cdcf772ed163 c9272c4f9fbe
Author: Ingo Molnar <mingo@elte.hu>
Date: Mon Jul 28 16:26:31 2008 +0200
Merge branch 'linus' into x86/cpu
Conflicts:
arch/x86/kernel/cpu/intel_cacheinfo.c
Signed-off-by: Ingo Molnar <mingo@elte.hu>
diff --cc arch/x86/kernel/cpu/intel_cacheinfo.c
index 535d662716de,650d40f7912b..d763d24187c2
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@@ -511,8 -489,8 +511,8 @@@ static void __cpuinit cache_remove_shar
int sibling;
this_leaf = CPUID4_INFO_IDX(cpu, index);
- for_each_cpu_mask(sibling, this_leaf->shared_cpu_map) {
+ for_each_cpu_mask_nr(sibling, this_leaf->shared_cpu_map) {
- sibling_leaf = CPUID4_INFO_IDX(sibling, index);
+ sibling_leaf = CPUID4_INFO_IDX(sibling, index);
cpu_clear(cpu, sibling_leaf->shared_cpu_map);
}
}
commit cdcf772ed163651cacac8098b4974aba7f9e1c73
Author: Ingo Molnar <mingo@elte.hu>
Date: Mon Jul 28 16:20:08 2008 +0200
x86 l3 cache index disable for 2 6 26 fix
Signed-off-by: Ingo Molnar <mingo@elte.hu>
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index a0c6c6ffed46..535d662716de 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -1,8 +1,8 @@
/*
- * Routines to indentify caches on Intel CPU.
+ * Routines to indentify caches on Intel CPU.
*
- * Changes:
- * Venkatesh Pallipadi : Adding cache identification through cpuid(4)
+ * Changes:
+ * Venkatesh Pallipadi : Adding cache identification through cpuid(4)
* Ashok Raj <ashok.raj@intel.com>: Work with CPU hotplug infrastructure.
* Andi Kleen / Andreas Herrmann : CPUID4 emulation on AMD.
*/
@@ -136,9 +136,9 @@ struct _cpuid4_info {
};
static struct pci_device_id k8_nb_id[] = {
- { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1103) },
- { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1203) },
- {}
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1103) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1203) },
+ {}
};
unsigned short num_cache_leaves;
@@ -190,9 +190,10 @@ static unsigned short assocs[] __cpuinitdata = {
static unsigned char levels[] __cpuinitdata = { 1, 1, 2, 3 };
static unsigned char types[] __cpuinitdata = { 1, 2, 3, 3 };
-static void __cpuinit amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
- union _cpuid4_leaf_ebx *ebx,
- union _cpuid4_leaf_ecx *ecx)
+static void __cpuinit
+amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
+ union _cpuid4_leaf_ebx *ebx,
+ union _cpuid4_leaf_ecx *ecx)
{
unsigned dummy;
unsigned line_size, lines_per_tag, assoc, size_in_kb;
@@ -264,7 +265,7 @@ amd_check_l3_disable(int index, struct _cpuid4_info *this_leaf)
{
if (index < 3)
return;
- this_leaf->can_disable = 1;
+ this_leaf->can_disable = 1;
}
static int
@@ -474,7 +475,7 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
/* pointer to _cpuid4_info array (for each cache leaf) */
static DEFINE_PER_CPU(struct _cpuid4_info *, cpuid4_info);
-#define CPUID4_INFO_IDX(x, y) (&((per_cpu(cpuid4_info, x))[y]))
+#define CPUID4_INFO_IDX(x, y) (&((per_cpu(cpuid4_info, x))[y]))
#ifdef CONFIG_SMP
static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
@@ -511,7 +512,7 @@ static void __cpuinit cache_remove_shared_cpu_map(unsigned int cpu, int index)
this_leaf = CPUID4_INFO_IDX(cpu, index);
for_each_cpu_mask(sibling, this_leaf->shared_cpu_map) {
- sibling_leaf = CPUID4_INFO_IDX(sibling, index);
+ sibling_leaf = CPUID4_INFO_IDX(sibling, index);
cpu_clear(cpu, sibling_leaf->shared_cpu_map);
}
}
@@ -593,7 +594,7 @@ struct _index_kobject {
/* pointer to array of kobjects for cpuX/cache/indexY */
static DEFINE_PER_CPU(struct _index_kobject *, index_kobject);
-#define INDEX_KOBJECT_PTR(x, y) (&((per_cpu(index_kobject, x))[y]))
+#define INDEX_KOBJECT_PTR(x, y) (&((per_cpu(index_kobject, x))[y]))
#define show_one_plus(file_name, object, val) \
static ssize_t show_##file_name \
@@ -675,7 +676,7 @@ static struct pci_dev *get_k8_northbridge(int node)
if (!dev)
break;
}
- return dev;
+ return dev;
}
static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf)
@@ -736,7 +737,7 @@ store_cache_disable(struct _cpuid4_info *this_leaf, const char *buf,
printk(KERN_ERR "Attempting AMD northbridge operation on a system with no northbridge\n");
return -EINVAL;
}
-
+
pci_write_config_dword(dev, 0x1BC + index * 4, val & ~0x40000000);
wbinvd();
pci_write_config_dword(dev, 0x1BC + index * 4, val);
@@ -789,7 +790,7 @@ static ssize_t show(struct kobject * kobj, struct attribute * attr, char * buf)
ret = fattr->show ?
fattr->show(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index),
buf) :
- 0;
+ 0;
return ret;
}
@@ -800,9 +801,9 @@ static ssize_t store(struct kobject * kobj, struct attribute * attr,
struct _index_kobject *this_leaf = to_object(kobj);
ssize_t ret;
- ret = fattr->store ?
- fattr->store(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index),
- buf, count) :
+ ret = fattr->store ?
+ fattr->store(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index),
+ buf, count) :
0;
return ret;
}
commit 7a4983bb5f94f6521aa3236fe5c035cf9bef543f
Author: Ingo Molnar <mingo@elte.hu>
Date: Mon Jul 21 13:34:21 2008 +0200
x86: L3 cache index disable for 2.6.26, cleanups
No change in functionality.
Signed-off-by: Ingo Molnar <mingo@elte.hu>
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index d6ea50e270e0..a61c9e399ba9 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -253,14 +253,16 @@ static void __cpuinit amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
(ebx->split.ways_of_associativity + 1) - 1;
}
-static void __cpuinit amd_check_l3_disable(int index, struct _cpuid4_info *this_leaf)
+static void __cpuinit
+amd_check_l3_disable(int index, struct _cpuid4_info *this_leaf)
{
if (index < 3)
return;
this_leaf->can_disable = 1;
}
-static int __cpuinit cpuid4_cache_lookup(int index, struct _cpuid4_info *this_leaf)
+static int
+__cpuinit cpuid4_cache_lookup(int index, struct _cpuid4_info *this_leaf)
{
union _cpuid4_leaf_eax eax;
union _cpuid4_leaf_ebx ebx;
@@ -271,19 +273,20 @@ static int __cpuinit cpuid4_cache_lookup(int index, struct _cpuid4_info *this_le
amd_cpuid4(index, &eax, &ebx, &ecx);
if (boot_cpu_data.x86 >= 0x10)
amd_check_l3_disable(index, this_leaf);
-
- } else
- cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &edx);
+ } else {
+ cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &edx);
+ }
+
if (eax.split.type == CACHE_TYPE_NULL)
return -EIO; /* better error ? */
this_leaf->eax = eax;
this_leaf->ebx = ebx;
this_leaf->ecx = ecx;
- this_leaf->size = (ecx.split.number_of_sets + 1) *
- (ebx.split.coherency_line_size + 1) *
- (ebx.split.physical_line_partition + 1) *
- (ebx.split.ways_of_associativity + 1);
+ this_leaf->size = (ecx.split.number_of_sets + 1) *
+ (ebx.split.coherency_line_size + 1) *
+ (ebx.split.physical_line_partition + 1) *
+ (ebx.split.ways_of_associativity + 1);
return 0;
}
@@ -649,59 +652,63 @@ static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf) {
}
}
-#define to_object(k) container_of(k, struct _index_kobject, kobj)
-#define to_attr(a) container_of(a, struct _cache_attr, attr)
+#define to_object(k) container_of(k, struct _index_kobject, kobj)
+#define to_attr(a) container_of(a, struct _cache_attr, attr)
static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf)
{
- struct pci_dev *dev;
- if (this_leaf->can_disable) {
- int i;
- ssize_t ret = 0;
- int node = cpu_to_node(first_cpu(this_leaf->shared_cpu_map));
- dev = k8_northbridges[node];
-
- for (i = 0; i < 2; i++) {
- unsigned int reg;
- pci_read_config_dword(dev, 0x1BC + i * 4, ®);
- ret += sprintf(buf, "%sEntry: %d\n", buf, i);
- ret += sprintf(buf, "%sReads: %s\tNew Entries: %s\n",
- buf,
- reg & 0x80000000 ? "Disabled" : "Allowed",
- reg & 0x40000000 ? "Disabled" : "Allowed");
- ret += sprintf(buf, "%sSubCache: %x\tIndex: %x\n", buf,
- (reg & 0x30000) >> 16, reg & 0xfff);
+ int node = cpu_to_node(first_cpu(this_leaf->shared_cpu_map));
+ struct pci_dev *dev = k8_northbridges[node];
+ ssize_t ret = 0;
+ int i;
- }
- return ret;
+ if (!this_leaf->can_disable)
+ return sprintf(buf, "Feature not enabled\n");
+
+ for (i = 0; i < 2; i++) {
+ unsigned int reg;
+
+ pci_read_config_dword(dev, 0x1BC + i * 4, ®);
+
+ ret += sprintf(buf, "%sEntry: %d\n", buf, i);
+ ret += sprintf(buf, "%sReads: %s\tNew Entries: %s\n",
+ buf,
+ reg & 0x80000000 ? "Disabled" : "Allowed",
+ reg & 0x40000000 ? "Disabled" : "Allowed");
+ ret += sprintf(buf, "%sSubCache: %x\tIndex: %x\n",
+ buf, (reg & 0x30000) >> 16, reg & 0xfff);
}
- return sprintf(buf, "Feature not enabled\n");
+ return ret;
}
-static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf, const char *buf, size_t count)
+static ssize_t
+store_cache_disable(struct _cpuid4_info *this_leaf, const char *buf,
+ size_t count)
{
- struct pci_dev *dev;
- if (this_leaf->can_disable) {
- /* write the MSR value */
- unsigned int ret;
- unsigned int index, val;
- int node = cpu_to_node(first_cpu(this_leaf->shared_cpu_map));
- dev = k8_northbridges[node];
-
- if (strlen(buf) > 15)
- return -EINVAL;
- ret = sscanf(buf, "%x %x", &index, &val);
- if (ret != 2)
- return -EINVAL;
- if (index > 1)
- return -EINVAL;
- val |= 0xc0000000;
- pci_write_config_dword(dev, 0x1BC + index * 4, val & ~0x40000000);
- wbinvd();
- pci_write_config_dword(dev, 0x1BC + index * 4, val);
- return 1;
- }
- return 0;
+ int node = cpu_to_node(first_cpu(this_leaf->shared_cpu_map));
+ struct pci_dev *dev = k8_northbridges[node];
+ unsigned int ret, index, val;
+
+ if (!this_leaf->can_disable)
+ return 0;
+
+ /* write the MSR value */
+
+ if (strlen(buf) > 15)
+ return -EINVAL;
+
+ ret = sscanf(buf, "%x %x", &index, &val);
+ if (ret != 2)
+ return -EINVAL;
+ if (index > 1)
+ return -EINVAL;
+
+ val |= 0xc0000000;
+ pci_write_config_dword(dev, 0x1BC + index * 4, val & ~0x40000000);
+ wbinvd();
+ pci_write_config_dword(dev, 0x1BC + index * 4, val);
+
+ return 1;
}
struct _cache_attr {
commit a403e45c3b678211ee3b7225dbb924921fb5ddd3
Merge: a05d2ebab280 d974ae379a2f
Author: Ingo Molnar <mingo@elte.hu>
Date: Mon Jul 28 15:07:54 2008 +0200
Merge core/lib: pick up memparse() change.
Merge branch 'core/lib' into x86/xen
commit 2106b531eaa2edd0c2dfa735a0556c08c7ba3c86
Merge: e338125b8a88 ba661292a2bc
Author: Ingo Molnar <mingo@elte.hu>
Date: Sun Jul 27 23:15:26 2008 +0200
Merge branch 'timers/urgent' of ssh://master.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip into timers/urgent
commit 3964cd3a6721f18ef1dd67b9a0a89dc5b36683b9
Author: Ingo Molnar <mingo@elte.hu>
Date: Sat Jul 26 19:35:20 2008 +0200
x86: visws_quirks, fix build error
fix:
arch/x86/kernel/visws_quirks.c: In function ‘visws_early_detect’:
arch/x86/kernel/visws_quirks.c:290: error: ‘skip_ioapic_setup’ undeclared (first use in this function)
arch/x86/kernel/visws_quirks.c:290: error: (Each undeclared identifier is reported only once
arch/x86/kernel/visws_quirks.c:290: error: for each function it appears in.)
Signed-off-by: Ingo Molnar <mingo@elte.hu>
diff --git a/arch/x86/kernel/visws_quirks.c b/arch/x86/kernel/visws_quirks.c
index 0c75691bcf5f..3059eb45a915 100644
--- a/arch/x86/kernel/visws_quirks.c
+++ b/arch/x86/kernel/visws_quirks.c
@@ -25,6 +25,7 @@
#include <asm/visws/cobalt.h>
#include <asm/visws/piix4.h>
#include <asm/arch_hooks.h>
+#include <asm/io_apic.h>
#include <asm/fixmap.h>
#include <asm/reboot.h>
#include <asm/setup.h>
commit c3cc99ff5d24e2eeaf7ec2032e720681916990e3
Merge: 38ffbe66d590 024e8ac04453
Author: Ingo Molnar <mingo@elte.hu>
Date: Sat Jul 26 17:48:49 2008 +0200
Merge branch 'linus' into x86/xen